From: Paolo Bonzini <pbonzini@redhat.com>
To: Wanpeng Li <wanpeng.li@linux.intel.com>
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org
Subject: Re: [Qemu-devel] [PATCH] target-i386: Intel xsaves
Date: Tue, 02 Dec 2014 13:33:11 +0100 [thread overview]
Message-ID: <547DB187.60001@redhat.com> (raw)
In-Reply-To: <1417522773-57538-1-git-send-email-wanpeng.li@linux.intel.com>
On 02/12/2014 13:19, Wanpeng Li wrote:
> Add xsaves related definition, it also add corresponding part to
> kvm_get/put, and vmstate.
>
> Signed-off-by: Wanpeng Li <wanpeng.li@linux.intel.com>
> ---
> target-i386/cpu.h | 2 ++
> target-i386/kvm.c | 15 +++++++++++++++
> target-i386/machine.c | 3 ++-
> 3 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index 015f5b5..cff7433 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -389,6 +389,7 @@
> #define MSR_VM_HSAVE_PA 0xc0010117
>
> #define MSR_IA32_BNDCFGS 0x00000d90
> +#define MSR_IA32_XSS 0x00000da0
>
> #define XSTATE_FP (1ULL << 0)
> #define XSTATE_SSE (1ULL << 1)
> @@ -1019,6 +1020,7 @@ typedef struct CPUX86State {
> uint64_t xstate_bv;
>
> uint64_t xcr0;
> + uint64_t xss;
>
> TPRAccess tpr_access_type;
> } CPUX86State;
> diff --git a/target-i386/kvm.c b/target-i386/kvm.c
> index ccf36e8..c6fc417 100644
> --- a/target-i386/kvm.c
> +++ b/target-i386/kvm.c
> @@ -80,6 +80,7 @@ static bool has_msr_hv_hypercall;
> static bool has_msr_hv_vapic;
> static bool has_msr_hv_tsc;
> static bool has_msr_mtrr;
> +static bool has_msr_xss;
>
> static bool has_msr_architectural_pmu;
> static uint32_t num_architectural_pmu_counters;
> @@ -826,6 +827,10 @@ static int kvm_get_supported_msrs(KVMState *s)
> has_msr_bndcfgs = true;
> continue;
> }
> + if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
> + has_msr_xss = true;
> + continue;
> + }
> }
> }
>
> @@ -1224,6 +1229,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
> if (has_msr_bndcfgs) {
> kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
> }
> + if (has_msr_xss) {
> + kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);
> + }
> #ifdef TARGET_X86_64
> if (lm_capable_kernel) {
> kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
> @@ -1570,6 +1578,10 @@ static int kvm_get_msrs(X86CPU *cpu)
> if (has_msr_bndcfgs) {
> msrs[n++].index = MSR_IA32_BNDCFGS;
> }
> + if (has_msr_xss) {
> + msrs[n++].index = MSR_IA32_XSS;
> + }
> +
>
> if (!env->tsc_valid) {
> msrs[n++].index = MSR_IA32_TSC;
> @@ -1717,6 +1729,9 @@ static int kvm_get_msrs(X86CPU *cpu)
> case MSR_IA32_BNDCFGS:
> env->msr_bndcfgs = msrs[i].data;
> break;
> + case MSR_IA32_XSS:
> + env->xss = msrs[i].data;
> + break;
> default:
> if (msrs[i].index >= MSR_MC0_CTL &&
> msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
> diff --git a/target-i386/machine.c b/target-i386/machine.c
> index 1c13b14..43af33f 100644
> --- a/target-i386/machine.c
> +++ b/target-i386/machine.c
> @@ -689,7 +689,7 @@ static const VMStateDescription vmstate_avx512 = {
>
> VMStateDescription vmstate_x86_cpu = {
> .name = "cpu",
> - .version_id = 12,
> + .version_id = 13,
> .minimum_version_id = 3,
> .pre_save = cpu_pre_save,
> .post_load = cpu_post_load,
> @@ -786,6 +786,7 @@ VMStateDescription vmstate_x86_cpu = {
> VMSTATE_UINT64_V(env.xcr0, X86CPU, 12),
> VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12),
> VMSTATE_YMMH_REGS_VARS(env.ymmh_regs, X86CPU, CPU_NB_REGS, 12),
> + VMSTATE_UINT64_V(env.xss, X86CPU, 13),
> VMSTATE_END_OF_LIST()
> /* The above list is not sorted /wrt version numbers, watch out! */
> },
>
Please use a subsection instead of bumping the version number.
Otherwise looks good.
Thanks!
Paolo
prev parent reply other threads:[~2014-12-02 12:33 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-02 12:19 [Qemu-devel] [PATCH] target-i386: Intel xsaves Wanpeng Li
2014-12-02 12:33 ` Paolo Bonzini [this message]
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