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References: <mhng-a324878c-b61d-4d8d-80bf-e15404469ef7@palmer-si-x1c4>
From: Thomas Huth <thuth@redhat.com>
Message-ID: <547f1afb-cce5-e456-5466-87ba333859b8@redhat.com>
Date: Thu, 31 Jan 2019 07:39:35 +0100
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Subject: Re: [Qemu-devel] [PR RFC] RISC-V Patches for 3.2, Part 3
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To: Palmer Dabbelt <palmer@sifive.com>, eblake@redhat.com
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Peter Maydell <peter.maydell@linaro.org>

On 2019-01-30 20:01, Palmer Dabbelt wrote:
> On Wed, 30 Jan 2019 09:45:33 PST (-0800), eblake@redhat.com wrote:
>> On 1/30/19 11:35 AM, Palmer Dabbelt wrote:
>>> The following changes since commit
>>> 5385a5988c8a55bebdc878c05b96648579b5d6e0:
>>>
>>> =C2=A0 hw/virtio/virtio-balloon: zero-initialize the virtio_balloon_c=
onfig
>>> struct (2019-01-21 17:20:36 +0000)
>>>
>>> are available in the Git repository at:
>>>
>>> =C2=A0 git://github.com/palmer-dabbelt/qemu.git
>>> tags/riscv-for-master-3.2-part3
>>>
>>> for you to fetch changes up to 461ab9de46d085a37b0da6f096aadc4e0dda4d=
4c:
>>>
>>> =C2=A0 target/riscv: fix counter-enable checks in ctr() (2019-01-29
>>> 11:33:38 -0800)
>>>
>>> ----------------------------------------------------------------
>>> RISC-V Patches for 3.2, Part 3
>>
>> There is no 3.2 release; the next release is named 4.0.=C2=A0 However,=
 if you
>> don't want to bother with sending a v2 pull request just to fix the
>> merge commit message, that's okay with me.
>=20
> Ah, sorry.=C2=A0 I think I'm just going to leave it as is, I'll get it =
right
> next time.

Also note that you used "PR RFC" in the title ... so not sure whether
Peter's scripts will catch this PR as a valid one...

 Thomas