* [Qemu-devel] [PATCH 0/3] x86 CPU model fixes
@ 2014-12-05 17:44 Paolo Bonzini
2014-12-05 17:44 ` [Qemu-devel] [PATCH 1/4] pc: add 2.3 machine types Paolo Bonzini
` (3 more replies)
0 siblings, 4 replies; 13+ messages in thread
From: Paolo Bonzini @ 2014-12-05 17:44 UTC (permalink / raw)
To: qemu-devel; +Cc: ehabkost
Most processors were lacking the VME flags. Haswell and Broadwell were
lacking two more. And Ivy Bridge was missing altogether.
Family/model/stepping for a low-end Xeon E3 v2 found on the SETI@Home CPU
list (http://setiathome.berkeley.edu/cpu_list.php), they also match the
Ivy Bridge Core i7 processor on which I tested the patch. The following
bare-metal features are missing in the guest:
dts acpi ss ht tm pbe arch_perfmon pebs bts xtopology nonstop_tsc
aperfmperf dtes64 monitor ds_cpl vmx smx est tm2 xtpr pdcm ida
arat epb pln pts dtherm tpr_shadow vnmi flexpriority ept vpid
... the absence of none of which is surprising.
Paolo
Paolo Bonzini (4):
pc: add 2.3 machine types
target-i386: add VME to all CPUs
target-i386: add f16c and rdrand to Haswell and Broadwell
target-i386: add Ivy Bridge CPU model
hw/i386/pc_piix.c | 47 +++++++++++++++++++++++++++++++++++---
hw/i386/pc_q35.c | 44 ++++++++++++++++++++++++++++++++---
target-i386/cpu.c | 68 ++++++++++++++++++++++++++++++++++++++++---------------
3 files changed, 135 insertions(+), 24 deletions(-)
--
1.8.3.1
^ permalink raw reply [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH 1/4] pc: add 2.3 machine types 2014-12-05 17:44 [Qemu-devel] [PATCH 0/3] x86 CPU model fixes Paolo Bonzini @ 2014-12-05 17:44 ` Paolo Bonzini 2014-12-05 18:14 ` Eduardo Habkost 2014-12-05 17:44 ` [Qemu-devel] [PATCH 2/4] target-i386: add VME to all CPUs Paolo Bonzini ` (2 subsequent siblings) 3 siblings, 1 reply; 13+ messages in thread From: Paolo Bonzini @ 2014-12-05 17:44 UTC (permalink / raw) To: qemu-devel; +Cc: ehabkost The next patch will differentiate them. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> --- hw/i386/pc_piix.c | 28 +++++++++++++++++++++++++--- hw/i386/pc_q35.c | 25 ++++++++++++++++++++++--- 2 files changed, 47 insertions(+), 6 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 741dffd..5ad23d0 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -303,6 +303,10 @@ static void pc_init_pci(MachineState *machine) pc_init1(machine, 1, 1); } +static void pc_compat_2_2(MachineState *machine) +{ +} + static void pc_compat_2_1(MachineState *machine) { PCMachineState *pcms = PC_MACHINE(machine); @@ -380,6 +384,12 @@ static void pc_compat_1_2(MachineState *machine) x86_cpu_compat_kvm_no_autoenable(FEAT_KVM, KVM_FEATURE_PV_EOI); } +static void pc_init_pci_2_2(MachineState *machine) +{ + pc_compat_2_2(machine); + pc_init_pci(machine); +} + static void pc_init_pci_2_1(MachineState *machine) { pc_compat_2_1(machine); @@ -473,6 +483,19 @@ static void pc_xen_hvm_init(MachineState *machine) .desc = "Standard PC (i440FX + PIIX, 1996)", \ .hot_add_cpu = pc_hot_add_cpu +#define PC_I440FX_2_3_MACHINE_OPTIONS \ + PC_I440FX_MACHINE_OPTIONS, \ + .default_machine_opts = "firmware=bios-256k.bin", \ + .default_display = "std" + +static QEMUMachine pc_i440fx_machine_v2_3 = { + PC_I440FX_2_3_MACHINE_OPTIONS, + .name = "pc-i440fx-2.3", + .alias = "pc", + .init = pc_init_pci, + .is_default = 1, +}; + #define PC_I440FX_2_2_MACHINE_OPTIONS \ PC_I440FX_MACHINE_OPTIONS, \ .default_machine_opts = "firmware=bios-256k.bin", \ @@ -481,9 +504,7 @@ static void pc_xen_hvm_init(MachineState *machine) static QEMUMachine pc_i440fx_machine_v2_2 = { PC_I440FX_2_2_MACHINE_OPTIONS, .name = "pc-i440fx-2.2", - .alias = "pc", - .init = pc_init_pci, - .is_default = 1, + .init = pc_init_pci_2_2, }; #define PC_I440FX_2_1_MACHINE_OPTIONS \ @@ -923,6 +944,7 @@ static QEMUMachine xenfv_machine = { static void pc_machine_init(void) { + qemu_register_pc_machine(&pc_i440fx_machine_v2_3); qemu_register_pc_machine(&pc_i440fx_machine_v2_2); qemu_register_pc_machine(&pc_i440fx_machine_v2_1); qemu_register_pc_machine(&pc_i440fx_machine_v2_0); diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index e9ba1a2..1ff3828 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -282,6 +282,10 @@ static void pc_q35_init(MachineState *machine) } } +static void pc_compat_2_2(MachineState *machine) +{ +} + static void pc_compat_2_1(MachineState *machine) { PCMachineState *pcms = PC_MACHINE(machine); @@ -329,6 +333,12 @@ static void pc_compat_1_4(MachineState *machine) x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ); } +static void pc_q35_init_2_2(MachineState *machine) +{ + pc_compat_2_2(machine); + pc_q35_init(machine); +} + static void pc_q35_init_2_1(MachineState *machine) { pc_compat_2_1(machine); @@ -372,16 +382,24 @@ static void pc_q35_init_1_4(MachineState *machine) .hot_add_cpu = pc_hot_add_cpu, \ .units_per_default_bus = 1 -#define PC_Q35_2_2_MACHINE_OPTIONS \ +#define PC_Q35_2_3_MACHINE_OPTIONS \ PC_Q35_MACHINE_OPTIONS, \ .default_machine_opts = "firmware=bios-256k.bin", \ .default_display = "std" +static QEMUMachine pc_q35_machine_v2_3 = { + PC_Q35_2_3_MACHINE_OPTIONS, + .name = "pc-q35-2.3", + .alias = "q35", + .init = pc_q35_init, +}; + +#define PC_Q35_2_2_MACHINE_OPTIONS PC_Q35_2_3_MACHINE_OPTIONS + static QEMUMachine pc_q35_machine_v2_2 = { PC_Q35_2_2_MACHINE_OPTIONS, .name = "pc-q35-2.2", - .alias = "q35", - .init = pc_q35_init, + .init = pc_q35_init_2_2, }; #define PC_Q35_2_1_MACHINE_OPTIONS \ @@ -460,6 +478,7 @@ static QEMUMachine pc_q35_machine_v1_4 = { static void pc_q35_machine_init(void) { + qemu_register_pc_machine(&pc_q35_machine_v2_3); qemu_register_pc_machine(&pc_q35_machine_v2_2); qemu_register_pc_machine(&pc_q35_machine_v2_1); qemu_register_pc_machine(&pc_q35_machine_v2_0); -- 1.8.3.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH 1/4] pc: add 2.3 machine types 2014-12-05 17:44 ` [Qemu-devel] [PATCH 1/4] pc: add 2.3 machine types Paolo Bonzini @ 2014-12-05 18:14 ` Eduardo Habkost 2014-12-05 18:18 ` Paolo Bonzini 0 siblings, 1 reply; 13+ messages in thread From: Eduardo Habkost @ 2014-12-05 18:14 UTC (permalink / raw) To: Paolo Bonzini; +Cc: qemu-devel On Fri, Dec 05, 2014 at 06:44:23PM +0100, Paolo Bonzini wrote: > The next patch will differentiate them. > > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> > --- > hw/i386/pc_piix.c | 28 +++++++++++++++++++++++++--- > hw/i386/pc_q35.c | 25 ++++++++++++++++++++++--- > 2 files changed, 47 insertions(+), 6 deletions(-) > > diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c > index 741dffd..5ad23d0 100644 > --- a/hw/i386/pc_piix.c > +++ b/hw/i386/pc_piix.c > @@ -303,6 +303,10 @@ static void pc_init_pci(MachineState *machine) > pc_init1(machine, 1, 1); > } > > +static void pc_compat_2_2(MachineState *machine) > +{ > +} > + > static void pc_compat_2_1(MachineState *machine) > { > PCMachineState *pcms = PC_MACHINE(machine); You need to make pc_compat_2_1() call pc_compat_2_2(). The same on pc_q35.c. > @@ -380,6 +384,12 @@ static void pc_compat_1_2(MachineState *machine) > x86_cpu_compat_kvm_no_autoenable(FEAT_KVM, KVM_FEATURE_PV_EOI); > } > > +static void pc_init_pci_2_2(MachineState *machine) > +{ > + pc_compat_2_2(machine); > + pc_init_pci(machine); > +} > + > static void pc_init_pci_2_1(MachineState *machine) > { > pc_compat_2_1(machine); > @@ -473,6 +483,19 @@ static void pc_xen_hvm_init(MachineState *machine) > .desc = "Standard PC (i440FX + PIIX, 1996)", \ > .hot_add_cpu = pc_hot_add_cpu > > +#define PC_I440FX_2_3_MACHINE_OPTIONS \ > + PC_I440FX_MACHINE_OPTIONS, \ > + .default_machine_opts = "firmware=bios-256k.bin", \ > + .default_display = "std" > + > +static QEMUMachine pc_i440fx_machine_v2_3 = { > + PC_I440FX_2_3_MACHINE_OPTIONS, > + .name = "pc-i440fx-2.3", > + .alias = "pc", > + .init = pc_init_pci, > + .is_default = 1, > +}; > + > #define PC_I440FX_2_2_MACHINE_OPTIONS \ > PC_I440FX_MACHINE_OPTIONS, \ I was going to suggest making PC_I440FX_2_2_MACHINE_OPTIONS reuse PC_I440FX_2_3_MACHINE_OPTIONS, but I think we have enough macro reuse mess here, and this is safer and simpler? > .default_machine_opts = "firmware=bios-256k.bin", \ > @@ -481,9 +504,7 @@ static void pc_xen_hvm_init(MachineState *machine) > static QEMUMachine pc_i440fx_machine_v2_2 = { > PC_I440FX_2_2_MACHINE_OPTIONS, > .name = "pc-i440fx-2.2", > - .alias = "pc", > - .init = pc_init_pci, > - .is_default = 1, > + .init = pc_init_pci_2_2, > }; > [...] -- Eduardo ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH 1/4] pc: add 2.3 machine types 2014-12-05 18:14 ` Eduardo Habkost @ 2014-12-05 18:18 ` Paolo Bonzini 0 siblings, 0 replies; 13+ messages in thread From: Paolo Bonzini @ 2014-12-05 18:18 UTC (permalink / raw) To: Eduardo Habkost; +Cc: qemu-devel On 05/12/2014 19:14, Eduardo Habkost wrote: >> > #define PC_I440FX_2_2_MACHINE_OPTIONS \ >> > PC_I440FX_MACHINE_OPTIONS, \ > I was going to suggest making PC_I440FX_2_2_MACHINE_OPTIONS reuse > PC_I440FX_2_3_MACHINE_OPTIONS, but I think we have enough macro reuse > mess here, and this is safer and simpler? Yeah, this is following for default_display what the file was already doing for default_machine_opts. Paolo ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Qemu-devel] [PATCH 2/4] target-i386: add VME to all CPUs 2014-12-05 17:44 [Qemu-devel] [PATCH 0/3] x86 CPU model fixes Paolo Bonzini 2014-12-05 17:44 ` [Qemu-devel] [PATCH 1/4] pc: add 2.3 machine types Paolo Bonzini @ 2014-12-05 17:44 ` Paolo Bonzini 2014-12-05 18:32 ` Eduardo Habkost 2014-12-05 17:44 ` [Qemu-devel] [PATCH 3/4] target-i386: add f16c and rdrand to Haswell and Broadwell Paolo Bonzini 2014-12-05 17:44 ` [Qemu-devel] [PATCH 4/4] target-i386: add Ivy Bridge CPU model Paolo Bonzini 3 siblings, 1 reply; 13+ messages in thread From: Paolo Bonzini @ 2014-12-05 17:44 UTC (permalink / raw) To: qemu-devel; +Cc: ehabkost vm86 mode extensions date back to the 486. All models should have them. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> --- hw/i386/pc_piix.c | 15 +++++++++++++++ hw/i386/pc_q35.c | 15 +++++++++++++++ target-i386/cpu.c | 30 +++++++++++++++--------------- 3 files changed, 45 insertions(+), 15 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 5ad23d0..3f1524e 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -305,6 +305,21 @@ static void pc_init_pci(MachineState *machine) static void pc_compat_2_2(MachineState *machine) { + x86_cpu_compat_set_features("kvm64", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("kvm32", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("coreduo", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Conroe", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Penryn", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Nehalem", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("SandyBridge", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Opteron_G1", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Opteron_G2", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Opteron_G3", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Opteron_G4", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Opteron_G5", FEAT_1_ECX, CPUID_EXT_VME, 0); } static void pc_compat_2_1(MachineState *machine) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 1ff3828..bec234a 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -284,6 +284,21 @@ static void pc_q35_init(MachineState *machine) static void pc_compat_2_2(MachineState *machine) { + x86_cpu_compat_set_features("kvm64", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("kvm32", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("coreduo", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Conroe", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Penryn", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Nehalem", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("SandyBridge", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Opteron_G1", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Opteron_G2", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Opteron_G3", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Opteron_G4", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Opteron_G5", FEAT_1_ECX, CPUID_EXT_VME, 0); } static void pc_compat_2_1(MachineState *machine) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index ef7d71c..136c457 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -760,9 +760,9 @@ static X86CPUDefinition builtin_x86_defs[] = { .family = 15, .model = 6, .stepping = 1, - /* Missing: CPUID_VME, CPUID_HT */ + /* Missing: CPUID_HT */ .features[FEAT_1_EDX] = - PPRO_FEATURES | + PPRO_FEATURES | CPUID_VME | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ @@ -802,7 +802,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 6, .stepping = 1, .features[FEAT_1_EDX] = - PPRO_FEATURES | + PPRO_FEATURES | CPUID_VME | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, .features[FEAT_1_ECX] = CPUID_EXT_SSE3, @@ -928,7 +928,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 15, .stepping = 3, .features[FEAT_1_EDX] = - CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | @@ -950,7 +950,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 23, .stepping = 3, .features[FEAT_1_EDX] = - CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | @@ -973,7 +973,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 26, .stepping = 3, .features[FEAT_1_EDX] = - CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | @@ -996,7 +996,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 44, .stepping = 1, .features[FEAT_1_EDX] = - CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | @@ -1020,7 +1020,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 42, .stepping = 1, .features[FEAT_1_EDX] = - CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | @@ -1049,7 +1049,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 60, .stepping = 1, .features[FEAT_1_EDX] = - CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | @@ -1084,7 +1084,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 61, .stepping = 2, .features[FEAT_1_EDX] = - CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | @@ -1120,7 +1120,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 6, .stepping = 1, .features[FEAT_1_EDX] = - CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | @@ -1145,7 +1145,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 6, .stepping = 1, .features[FEAT_1_EDX] = - CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | @@ -1173,7 +1173,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 6, .stepping = 1, .features[FEAT_1_EDX] = - CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | @@ -1203,7 +1203,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 1, .stepping = 2, .features[FEAT_1_EDX] = - CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | @@ -1238,7 +1238,7 @@ static X86CPUDefinition builtin_x86_defs[] = { .model = 2, .stepping = 0, .features[FEAT_1_EDX] = - CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | -- 1.8.3.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH 2/4] target-i386: add VME to all CPUs 2014-12-05 17:44 ` [Qemu-devel] [PATCH 2/4] target-i386: add VME to all CPUs Paolo Bonzini @ 2014-12-05 18:32 ` Eduardo Habkost 2014-12-05 18:36 ` Paolo Bonzini 0 siblings, 1 reply; 13+ messages in thread From: Eduardo Habkost @ 2014-12-05 18:32 UTC (permalink / raw) To: Paolo Bonzini; +Cc: qemu-devel On Fri, Dec 05, 2014 at 06:44:24PM +0100, Paolo Bonzini wrote: > vm86 mode extensions date back to the 486. All models should have > them. > > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> TCG doesn't support VME (that's probably why we didn't have it set on most CPU models), and I would like to eventually make check/enforce mode work on TCG as well. I was going to suggest adding it to kvm_default_features instead, but as we have existing models that have CPUID_VME already, let's be consistent and add it to all of them (and deal with TCG check/enforce mode later, if necessary). > --- > hw/i386/pc_piix.c | 15 +++++++++++++++ > hw/i386/pc_q35.c | 15 +++++++++++++++ > target-i386/cpu.c | 30 +++++++++++++++--------------- > 3 files changed, 45 insertions(+), 15 deletions(-) > > diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c > index 5ad23d0..3f1524e 100644 > --- a/hw/i386/pc_piix.c > +++ b/hw/i386/pc_piix.c > @@ -305,6 +305,21 @@ static void pc_init_pci(MachineState *machine) > > static void pc_compat_2_2(MachineState *machine) > { > + x86_cpu_compat_set_features("kvm64", FEAT_1_ECX, CPUID_EXT_VME, 0); qemu/hw/i386/pc_piix.c:313:54: error: ‘CPUID_EXT_VME’ undeclared (first use in this function) x86_cpu_compat_set_features("kvm64", FEAT_1_ECX, CPUID_EXT_VME, 0); > + x86_cpu_compat_set_features("kvm32", FEAT_1_ECX, CPUID_EXT_VME, 0); > + x86_cpu_compat_set_features("coreduo", FEAT_1_ECX, CPUID_EXT_VME, 0); > + x86_cpu_compat_set_features("Conroe", FEAT_1_ECX, CPUID_EXT_VME, 0); > + x86_cpu_compat_set_features("Penryn", FEAT_1_ECX, CPUID_EXT_VME, 0); > + x86_cpu_compat_set_features("Nehalem", FEAT_1_ECX, CPUID_EXT_VME, 0); > + x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, CPUID_EXT_VME, 0); > + x86_cpu_compat_set_features("SandyBridge", FEAT_1_ECX, CPUID_EXT_VME, 0); > + x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, CPUID_EXT_VME, 0); > + x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, CPUID_EXT_VME, 0); > + x86_cpu_compat_set_features("Opteron_G1", FEAT_1_ECX, CPUID_EXT_VME, 0); > + x86_cpu_compat_set_features("Opteron_G2", FEAT_1_ECX, CPUID_EXT_VME, 0); > + x86_cpu_compat_set_features("Opteron_G3", FEAT_1_ECX, CPUID_EXT_VME, 0); > + x86_cpu_compat_set_features("Opteron_G4", FEAT_1_ECX, CPUID_EXT_VME, 0); > + x86_cpu_compat_set_features("Opteron_G5", FEAT_1_ECX, CPUID_EXT_VME, 0); The features need to be _removed_ when running an older machine-type, not added. It should be: x86_cpu_compat_set_features(MODEL, FEAT_1_EDX, 0, CPUID_VME); But the list of CPU models is correct, and matches what is being changed on builtin_x86_defs[]. -- Eduardo ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH 2/4] target-i386: add VME to all CPUs 2014-12-05 18:32 ` Eduardo Habkost @ 2014-12-05 18:36 ` Paolo Bonzini 0 siblings, 0 replies; 13+ messages in thread From: Paolo Bonzini @ 2014-12-05 18:36 UTC (permalink / raw) To: Eduardo Habkost; +Cc: qemu-devel On 05/12/2014 19:32, Eduardo Habkost wrote: >> > vm86 mode extensions date back to the 486. All models should have >> > them. >> > >> > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> > TCG doesn't support VME (that's probably why we didn't have it set on > most CPU models), and I would like to eventually make check/enforce mode > work on TCG as well. > > I was going to suggest adding it to kvm_default_features instead, but as > we have existing models that have CPUID_VME already, let's be consistent > and add it to all of them (and deal with TCG check/enforce mode later, > if necessary). Yes, my thoughts as well. The weird thing is that we have it on the really old models that TCG ought to emulate almost completely, but not on the newer ones... We can add tcg_default_unset_features too. Paolo ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Qemu-devel] [PATCH 3/4] target-i386: add f16c and rdrand to Haswell and Broadwell 2014-12-05 17:44 [Qemu-devel] [PATCH 0/3] x86 CPU model fixes Paolo Bonzini 2014-12-05 17:44 ` [Qemu-devel] [PATCH 1/4] pc: add 2.3 machine types Paolo Bonzini 2014-12-05 17:44 ` [Qemu-devel] [PATCH 2/4] target-i386: add VME to all CPUs Paolo Bonzini @ 2014-12-05 17:44 ` Paolo Bonzini 2014-12-05 18:35 ` Eduardo Habkost 2014-12-05 17:44 ` [Qemu-devel] [PATCH 4/4] target-i386: add Ivy Bridge CPU model Paolo Bonzini 3 siblings, 1 reply; 13+ messages in thread From: Paolo Bonzini @ 2014-12-05 17:44 UTC (permalink / raw) To: qemu-devel; +Cc: ehabkost Both were added in Ivy Bridge (for which we do not have a CPU model yet!). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> --- hw/i386/pc_piix.c | 4 ++++ hw/i386/pc_q35.c | 4 ++++ target-i386/cpu.c | 4 ++-- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 3f1524e..cd9f917 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -320,6 +320,10 @@ static void pc_compat_2_2(MachineState *machine) x86_cpu_compat_set_features("Opteron_G3", FEAT_1_ECX, CPUID_EXT_VME, 0); x86_cpu_compat_set_features("Opteron_G4", FEAT_1_ECX, CPUID_EXT_VME, 0); x86_cpu_compat_set_features("Opteron_G5", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, CPUID_EXT_F16C, 0); + x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, CPUID_EXT_RDRAND, 0); + x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, CPUID_EXT_F16C, 0); + x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, CPUID_EXT_RDRAND, 0); } static void pc_compat_2_1(MachineState *machine) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index bec234a..f225276 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -299,6 +299,10 @@ static void pc_compat_2_2(MachineState *machine) x86_cpu_compat_set_features("Opteron_G3", FEAT_1_ECX, CPUID_EXT_VME, 0); x86_cpu_compat_set_features("Opteron_G4", FEAT_1_ECX, CPUID_EXT_VME, 0); x86_cpu_compat_set_features("Opteron_G5", FEAT_1_ECX, CPUID_EXT_VME, 0); + x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, CPUID_EXT_F16C, 0); + x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, CPUID_EXT_RDRAND, 0); + x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, CPUID_EXT_F16C, 0); + x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, CPUID_EXT_RDRAND, 0); } static void pc_compat_2_1(MachineState *machine) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 136c457..b2bb9a4 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -1060,7 +1060,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | - CPUID_EXT_PCID, + CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, .features[FEAT_8000_0001_EDX] = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, @@ -1095,7 +1095,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | - CPUID_EXT_PCID, + CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, .features[FEAT_8000_0001_EDX] = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, -- 1.8.3.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH 3/4] target-i386: add f16c and rdrand to Haswell and Broadwell 2014-12-05 17:44 ` [Qemu-devel] [PATCH 3/4] target-i386: add f16c and rdrand to Haswell and Broadwell Paolo Bonzini @ 2014-12-05 18:35 ` Eduardo Habkost 0 siblings, 0 replies; 13+ messages in thread From: Eduardo Habkost @ 2014-12-05 18:35 UTC (permalink / raw) To: Paolo Bonzini; +Cc: qemu-devel On Fri, Dec 05, 2014 at 06:44:25PM +0100, Paolo Bonzini wrote: > Both were added in Ivy Bridge (for which we do not have a CPU model > yet!). > > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> > --- > hw/i386/pc_piix.c | 4 ++++ > hw/i386/pc_q35.c | 4 ++++ > target-i386/cpu.c | 4 ++-- > 3 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c > index 3f1524e..cd9f917 100644 > --- a/hw/i386/pc_piix.c > +++ b/hw/i386/pc_piix.c > @@ -320,6 +320,10 @@ static void pc_compat_2_2(MachineState *machine) > x86_cpu_compat_set_features("Opteron_G3", FEAT_1_ECX, CPUID_EXT_VME, 0); > x86_cpu_compat_set_features("Opteron_G4", FEAT_1_ECX, CPUID_EXT_VME, 0); > x86_cpu_compat_set_features("Opteron_G5", FEAT_1_ECX, CPUID_EXT_VME, 0); > + x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, CPUID_EXT_F16C, 0); > + x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, CPUID_EXT_RDRAND, 0); > + x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, CPUID_EXT_F16C, 0); > + x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, CPUID_EXT_RDRAND, 0); The feature should be removed on older machine-types, not added. This should be: x86_cpu_compat_set_features(MODEL, FEAT_1_ECX, 0, CPUID_EXT_...) (You can also use CPUID_EXT_F16C|CPUID_EXT_RDRAND in a single x86_cpu_compat_set_features() call) -- Eduardo ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Qemu-devel] [PATCH 4/4] target-i386: add Ivy Bridge CPU model 2014-12-05 17:44 [Qemu-devel] [PATCH 0/3] x86 CPU model fixes Paolo Bonzini ` (2 preceding siblings ...) 2014-12-05 17:44 ` [Qemu-devel] [PATCH 3/4] target-i386: add f16c and rdrand to Haswell and Broadwell Paolo Bonzini @ 2014-12-05 17:44 ` Paolo Bonzini 2014-12-05 18:36 ` Eduardo Habkost 2014-12-05 18:58 ` Eduardo Habkost 3 siblings, 2 replies; 13+ messages in thread From: Paolo Bonzini @ 2014-12-05 17:44 UTC (permalink / raw) To: qemu-devel; +Cc: ehabkost Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> --- target-i386/cpu.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index b2bb9a4..7767564 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -1039,7 +1039,39 @@ static X86CPUDefinition builtin_x86_defs[] = { .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, .xlevel = 0x8000000A, - .model_id = "Intel Xeon E312xx (Sandy Bridge)", + .model_id = "Intel Xeon E3-12xx (Sandy Bridge)", + }, + { + .name = "IvyBridge", + .level = 0xd, + .vendor = CPUID_VENDOR_INTEL, + .family = 6, + .model = 58, + .stepping = 9, + .features[FEAT_1_EDX] = + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .features[FEAT_1_ECX] = + CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | + CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | + CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | + CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, + .features[FEAT_7_0_EBX] = + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | + CPUID_7_0_EBX_ERMS, + .features[FEAT_8000_0001_EDX] = + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | + CPUID_EXT2_SYSCALL, + .features[FEAT_8000_0001_ECX] = + CPUID_EXT3_LAHF_LM, + .features[FEAT_XSAVE] = + CPUID_XSAVE_XSAVEOPT, + .xlevel = 0x8000000A, + .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", }, { .name = "Haswell", -- 1.8.3.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH 4/4] target-i386: add Ivy Bridge CPU model 2014-12-05 17:44 ` [Qemu-devel] [PATCH 4/4] target-i386: add Ivy Bridge CPU model Paolo Bonzini @ 2014-12-05 18:36 ` Eduardo Habkost 2014-12-05 18:39 ` Paolo Bonzini 2014-12-05 18:58 ` Eduardo Habkost 1 sibling, 1 reply; 13+ messages in thread From: Eduardo Habkost @ 2014-12-05 18:36 UTC (permalink / raw) To: Paolo Bonzini; +Cc: qemu-devel On Fri, Dec 05, 2014 at 06:44:26PM +0100, Paolo Bonzini wrote: > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> > --- > target-i386/cpu.c | 34 +++++++++++++++++++++++++++++++++- > 1 file changed, 33 insertions(+), 1 deletion(-) > > diff --git a/target-i386/cpu.c b/target-i386/cpu.c > index b2bb9a4..7767564 100644 > --- a/target-i386/cpu.c > +++ b/target-i386/cpu.c > @@ -1039,7 +1039,39 @@ static X86CPUDefinition builtin_x86_defs[] = { > .features[FEAT_XSAVE] = > CPUID_XSAVE_XSAVEOPT, > .xlevel = 0x8000000A, > - .model_id = "Intel Xeon E312xx (Sandy Bridge)", > + .model_id = "Intel Xeon E3-12xx (Sandy Bridge)", ABI change. Can we do that in a separate patch? -- Eduardo ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH 4/4] target-i386: add Ivy Bridge CPU model 2014-12-05 18:36 ` Eduardo Habkost @ 2014-12-05 18:39 ` Paolo Bonzini 0 siblings, 0 replies; 13+ messages in thread From: Paolo Bonzini @ 2014-12-05 18:39 UTC (permalink / raw) To: Eduardo Habkost; +Cc: qemu-devel On 05/12/2014 19:36, Eduardo Habkost wrote: > On Fri, Dec 05, 2014 at 06:44:26PM +0100, Paolo Bonzini wrote: >> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> >> --- >> target-i386/cpu.c | 34 +++++++++++++++++++++++++++++++++- >> 1 file changed, 33 insertions(+), 1 deletion(-) >> >> diff --git a/target-i386/cpu.c b/target-i386/cpu.c >> index b2bb9a4..7767564 100644 >> --- a/target-i386/cpu.c >> +++ b/target-i386/cpu.c >> @@ -1039,7 +1039,39 @@ static X86CPUDefinition builtin_x86_defs[] = { >> .features[FEAT_XSAVE] = >> CPUID_XSAVE_XSAVEOPT, >> .xlevel = 0x8000000A, >> - .model_id = "Intel Xeon E312xx (Sandy Bridge)", >> + .model_id = "Intel Xeon E3-12xx (Sandy Bridge)", > > ABI change. Can we do that in a separate patch? We can just leave the typo in, I didn't know this was an ABI change. Paolo ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH 4/4] target-i386: add Ivy Bridge CPU model 2014-12-05 17:44 ` [Qemu-devel] [PATCH 4/4] target-i386: add Ivy Bridge CPU model Paolo Bonzini 2014-12-05 18:36 ` Eduardo Habkost @ 2014-12-05 18:58 ` Eduardo Habkost 1 sibling, 0 replies; 13+ messages in thread From: Eduardo Habkost @ 2014-12-05 18:58 UTC (permalink / raw) To: Paolo Bonzini; +Cc: qemu-devel On Fri, Dec 05, 2014 at 06:44:26PM +0100, Paolo Bonzini wrote: > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> For reference, this is the delta from SandyBridge: model = 58; stepping = 9; features[FEAT_1_ECX] |= CPUID_EXT_F16C | CPUID_EXT_RDRAND; features[FEAT_7_0_EBX] |= CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS; This matches what I see in a real CPU with family/model/stepping IDs 6/58/9. Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> > --- > target-i386/cpu.c | 34 +++++++++++++++++++++++++++++++++- > 1 file changed, 33 insertions(+), 1 deletion(-) > > diff --git a/target-i386/cpu.c b/target-i386/cpu.c > index b2bb9a4..7767564 100644 > --- a/target-i386/cpu.c > +++ b/target-i386/cpu.c > @@ -1039,7 +1039,39 @@ static X86CPUDefinition builtin_x86_defs[] = { > .features[FEAT_XSAVE] = > CPUID_XSAVE_XSAVEOPT, > .xlevel = 0x8000000A, > - .model_id = "Intel Xeon E312xx (Sandy Bridge)", > + .model_id = "Intel Xeon E3-12xx (Sandy Bridge)", > + }, > + { > + .name = "IvyBridge", > + .level = 0xd, > + .vendor = CPUID_VENDOR_INTEL, > + .family = 6, > + .model = 58, > + .stepping = 9, > + .features[FEAT_1_EDX] = > + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | > + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | > + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > + CPUID_DE | CPUID_FP87, > + .features[FEAT_1_ECX] = > + CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | > + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | > + CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | > + CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | > + CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, > + .features[FEAT_7_0_EBX] = > + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | > + CPUID_7_0_EBX_ERMS, > + .features[FEAT_8000_0001_EDX] = > + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | > + CPUID_EXT2_SYSCALL, > + .features[FEAT_8000_0001_ECX] = > + CPUID_EXT3_LAHF_LM, > + .features[FEAT_XSAVE] = > + CPUID_XSAVE_XSAVEOPT, > + .xlevel = 0x8000000A, > + .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", > }, > { > .name = "Haswell", > -- > 1.8.3.1 > -- Eduardo ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2014-12-05 18:58 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-12-05 17:44 [Qemu-devel] [PATCH 0/3] x86 CPU model fixes Paolo Bonzini 2014-12-05 17:44 ` [Qemu-devel] [PATCH 1/4] pc: add 2.3 machine types Paolo Bonzini 2014-12-05 18:14 ` Eduardo Habkost 2014-12-05 18:18 ` Paolo Bonzini 2014-12-05 17:44 ` [Qemu-devel] [PATCH 2/4] target-i386: add VME to all CPUs Paolo Bonzini 2014-12-05 18:32 ` Eduardo Habkost 2014-12-05 18:36 ` Paolo Bonzini 2014-12-05 17:44 ` [Qemu-devel] [PATCH 3/4] target-i386: add f16c and rdrand to Haswell and Broadwell Paolo Bonzini 2014-12-05 18:35 ` Eduardo Habkost 2014-12-05 17:44 ` [Qemu-devel] [PATCH 4/4] target-i386: add Ivy Bridge CPU model Paolo Bonzini 2014-12-05 18:36 ` Eduardo Habkost 2014-12-05 18:39 ` Paolo Bonzini 2014-12-05 18:58 ` Eduardo Habkost
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