* [Qemu-devel] [PATCH] target-mips: Fix DisasContext's ulri member initialization
@ 2014-12-02 22:31 Maciej W. Rozycki
2014-12-11 15:37 ` Leon Alrae
0 siblings, 1 reply; 2+ messages in thread
From: Maciej W. Rozycki @ 2014-12-02 22:31 UTC (permalink / raw)
To: qemu-devel; +Cc: Leon Alrae, Aurelien Jarno
Set DisasContext's ulri member to 0 or 1 as with other bool members.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
---
qemu-mips-disas-ulri.diff
Index: qemu-git-trunk/target-mips/translate.c
===================================================================
--- qemu-git-trunk.orig/target-mips/translate.c 2014-12-02 21:28:17.528936640 +0000
+++ qemu-git-trunk/target-mips/translate.c 2014-12-02 21:28:41.028928249 +0000
@@ -19114,7 +19114,7 @@ gen_intermediate_code_internal(MIPSCPU *
ctx.bp = (env->CP0_Config3 >> CP0C3_BP) & 1;
/* Restore delay slot state from the tb context. */
ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */
- ctx.ulri = env->CP0_Config3 & (1 << CP0C3_ULRI);
+ ctx.ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;
restore_cpu_state(env, &ctx);
#ifdef CONFIG_USER_ONLY
ctx.mem_idx = MIPS_HFLAG_UM;
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [Qemu-devel] [PATCH] target-mips: Fix DisasContext's ulri member initialization
2014-12-02 22:31 [Qemu-devel] [PATCH] target-mips: Fix DisasContext's ulri member initialization Maciej W. Rozycki
@ 2014-12-11 15:37 ` Leon Alrae
0 siblings, 0 replies; 2+ messages in thread
From: Leon Alrae @ 2014-12-11 15:37 UTC (permalink / raw)
To: Maciej W. Rozycki, qemu-devel; +Cc: Aurelien Jarno
On 02/12/2014 22:31, Maciej W. Rozycki wrote:
> Set DisasContext's ulri member to 0 or 1 as with other bool members.
>
> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
> ---
> qemu-mips-disas-ulri.diff
> Index: qemu-git-trunk/target-mips/translate.c
> ===================================================================
> --- qemu-git-trunk.orig/target-mips/translate.c 2014-12-02 21:28:17.528936640 +0000
> +++ qemu-git-trunk/target-mips/translate.c 2014-12-02 21:28:41.028928249 +0000
> @@ -19114,7 +19114,7 @@ gen_intermediate_code_internal(MIPSCPU *
> ctx.bp = (env->CP0_Config3 >> CP0C3_BP) & 1;
> /* Restore delay slot state from the tb context. */
> ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */
> - ctx.ulri = env->CP0_Config3 & (1 << CP0C3_ULRI);
> + ctx.ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;
> restore_cpu_state(env, &ctx);
> #ifdef CONFIG_USER_ONLY
> ctx.mem_idx = MIPS_HFLAG_UM;
>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
^ permalink raw reply [flat|nested] 2+ messages in thread
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