From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51660) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XzSAx-0001Iy-Mb for qemu-devel@nongnu.org; Fri, 12 Dec 2014 10:30:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XzSAt-0002yf-3P for qemu-devel@nongnu.org; Fri, 12 Dec 2014 10:30:39 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:39089) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XzSAs-0002yW-TS for qemu-devel@nongnu.org; Fri, 12 Dec 2014 10:30:35 -0500 Message-ID: <548B1838.9040309@mail.uni-paderborn.de> Date: Fri, 12 Dec 2014 16:30:48 +0000 From: Bastian Koppelmann MIME-Version: 1.0 References: <1418393430-12336-1-git-send-email-alexander.zuepke@hs-rm.de> <5e864091-ecd0-4a22-abbb-be8c9cd28585@EXCHANGE-4K.hds.local> In-Reply-To: <5e864091-ecd0-4a22-abbb-be8c9cd28585@EXCHANGE-4K.hds.local> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 3/4] target-tricore: add missing 64-bit MOV in RLC format List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alex Zuepke , qemu-devel@nongnu.org On 12/12/2014 02:10 PM, Alex Zuepke wrote: > Signed-off-by: Alex Zuepke > --- > target-tricore/translate.c | 12 ++++++++++++ > target-tricore/tricore-opcodes.h | 1 + > 2 files changed, 13 insertions(+) > > diff --git a/target-tricore/translate.c b/target-tricore/translate.c > index c132223..e3eeedb 100644 > --- a/target-tricore/translate.c > +++ b/target-tricore/translate.c > @@ -3781,6 +3781,17 @@ static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx, > case OPC1_32_RLC_MOV: > tcg_gen_movi_tl(cpu_gpr_d[r2], const16); > break; > + case OPC1_32_RLC_MOV_64: > + if (tricore_feature(env, TRICORE_FEATURE_16)) { > + if ((r2 & 0x1) != 0) { > + /* TODO: raise OPD trap */ > + } This reminds me, that there should be a mechanism, which can create traps for all instructions that use two 32bit regs as one 64bit one. > + tcg_gen_movi_tl(cpu_gpr_d[r2], const16); > + tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15); > + } else { > + /* TODO: raise illegal opcode trap */ > + } > + break; > case OPC1_32_RLC_MOV_U: > const16 = MASK_OP_RLC_CONST16(ctx->opcode); > tcg_gen_movi_tl(cpu_gpr_d[r2], const16); > @@ -4021,6 +4032,7 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) > case OPC1_32_RLC_ADDIH_A: > case OPC1_32_RLC_MFCR: > case OPC1_32_RLC_MOV: > + case OPC1_32_RLC_MOV_64: > case OPC1_32_RLC_MOV_U: > case OPC1_32_RLC_MOV_H: > case OPC1_32_RLC_MOVH_A: > diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h > index 7aa6aed..a76a7e4 100644 > --- a/target-tricore/tricore-opcodes.h > +++ b/target-tricore/tricore-opcodes.h > @@ -487,6 +487,7 @@ enum { > OPC1_32_RLC_ADDIH_A = 0x11, > OPC1_32_RLC_MFCR = 0x4d, > OPC1_32_RLC_MOV = 0x3b, > + OPC1_32_RLC_MOV_64 = 0xfb, /* 1.6 only */ > OPC1_32_RLC_MOV_U = 0xbb, > OPC1_32_RLC_MOV_H = 0x7b, > OPC1_32_RLC_MOVH_A = 0x91, Looks good to me anyway. Reviewed-by: Bastian Koppelmann