* [Qemu-devel] [PATCH 1/4] target-tricore: fix offset masking in BOL format
[not found] <1418393430-12336-1-git-send-email-alexander.zuepke@hs-rm.de>
@ 2014-12-12 14:10 ` Alex Zuepke
2014-12-12 16:26 ` Bastian Koppelmann
2014-12-12 14:10 ` [Qemu-devel] [PATCH 2/4] target-tricore: typo " Alex Zuepke
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Alex Zuepke @ 2014-12-12 14:10 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, Alex Zuepke
Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de>
---
target-tricore/tricore-opcodes.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
index 0a9122c..70ac5ff 100644
--- a/target-tricore/tricore-opcodes.h
+++ b/target-tricore/tricore-opcodes.h
@@ -114,7 +114,7 @@
/* BOL Format */
#define MASK_OP_BOL_OFF16(op) ((MASK_BITS_SHIFT(op, 16, 21) + \
(MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
- (MASK_BITS_SHIFT(op, 22, 27) >> 10))
+ (MASK_BITS_SHIFT(op, 22, 27) << 10))
#define MASK_OP_BOL_OFF16_SEXT(op) ((MASK_BITS_SHIFT(op, 16, 21) + \
(MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
(MASK_BITS_SHIFT_SEXT(op, 22, 27) << 10))
--
1.7.9.5
^ permalink raw reply related [flat|nested] 8+ messages in thread* [Qemu-devel] [PATCH 2/4] target-tricore: typo in BOL format
[not found] <1418393430-12336-1-git-send-email-alexander.zuepke@hs-rm.de>
2014-12-12 14:10 ` [Qemu-devel] [PATCH 1/4] target-tricore: fix offset masking in BOL format Alex Zuepke
@ 2014-12-12 14:10 ` Alex Zuepke
2014-12-12 16:26 ` Bastian Koppelmann
2014-12-12 14:10 ` [Qemu-devel] [PATCH 3/4] target-tricore: add missing 64-bit MOV in RLC format Alex Zuepke
2014-12-12 14:10 ` [Qemu-devel] [PATCH 4/4] target-tricore: pretty-print register dump and show more status registers Alex Zuepke
3 siblings, 1 reply; 8+ messages in thread
From: Alex Zuepke @ 2014-12-12 14:10 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, Alex Zuepke
Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de>
---
target-tricore/translate.c | 4 ++--
target-tricore/tricore-opcodes.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 65abf45..c132223 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -3203,7 +3203,7 @@ static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1)
tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL);
tcg_temp_free(temp);
break;
- case OPC1_32_BOL_LD_W_LONFOFF:
+ case OPC1_32_BOL_LD_W_LONGOFF:
temp = tcg_temp_new();
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL);
@@ -3930,7 +3930,7 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
break;
/* BOL-format */
case OPC1_32_BOL_LD_A_LONGOFF:
- case OPC1_32_BOL_LD_W_LONFOFF:
+ case OPC1_32_BOL_LD_W_LONGOFF:
case OPC1_32_BOL_LEA_LONGOFF:
case OPC1_32_BOL_ST_W_LONGOFF:
case OPC1_32_BOL_ST_A_LONGOFF:
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
index 70ac5ff..7aa6aed 100644
--- a/target-tricore/tricore-opcodes.h
+++ b/target-tricore/tricore-opcodes.h
@@ -447,7 +447,7 @@ enum {
OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR = 0x69,
/* BOL Format */
OPC1_32_BOL_LD_A_LONGOFF = 0x99,
- OPC1_32_BOL_LD_W_LONFOFF = 0x19,
+ OPC1_32_BOL_LD_W_LONGOFF = 0x19,
OPC1_32_BOL_LEA_LONGOFF = 0xd9,
OPC1_32_BOL_ST_W_LONGOFF = 0x59,
OPC1_32_BOL_ST_A_LONGOFF = 0xb5, /* 1.6 only */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 8+ messages in thread* [Qemu-devel] [PATCH 3/4] target-tricore: add missing 64-bit MOV in RLC format
[not found] <1418393430-12336-1-git-send-email-alexander.zuepke@hs-rm.de>
2014-12-12 14:10 ` [Qemu-devel] [PATCH 1/4] target-tricore: fix offset masking in BOL format Alex Zuepke
2014-12-12 14:10 ` [Qemu-devel] [PATCH 2/4] target-tricore: typo " Alex Zuepke
@ 2014-12-12 14:10 ` Alex Zuepke
2014-12-12 16:30 ` Bastian Koppelmann
2014-12-12 14:10 ` [Qemu-devel] [PATCH 4/4] target-tricore: pretty-print register dump and show more status registers Alex Zuepke
3 siblings, 1 reply; 8+ messages in thread
From: Alex Zuepke @ 2014-12-12 14:10 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, Alex Zuepke
Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de>
---
target-tricore/translate.c | 12 ++++++++++++
target-tricore/tricore-opcodes.h | 1 +
2 files changed, 13 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index c132223..e3eeedb 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -3781,6 +3781,17 @@ static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx,
case OPC1_32_RLC_MOV:
tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
break;
+ case OPC1_32_RLC_MOV_64:
+ if (tricore_feature(env, TRICORE_FEATURE_16)) {
+ if ((r2 & 0x1) != 0) {
+ /* TODO: raise OPD trap */
+ }
+ tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
+ tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15);
+ } else {
+ /* TODO: raise illegal opcode trap */
+ }
+ break;
case OPC1_32_RLC_MOV_U:
const16 = MASK_OP_RLC_CONST16(ctx->opcode);
tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
@@ -4021,6 +4032,7 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
case OPC1_32_RLC_ADDIH_A:
case OPC1_32_RLC_MFCR:
case OPC1_32_RLC_MOV:
+ case OPC1_32_RLC_MOV_64:
case OPC1_32_RLC_MOV_U:
case OPC1_32_RLC_MOV_H:
case OPC1_32_RLC_MOVH_A:
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
index 7aa6aed..a76a7e4 100644
--- a/target-tricore/tricore-opcodes.h
+++ b/target-tricore/tricore-opcodes.h
@@ -487,6 +487,7 @@ enum {
OPC1_32_RLC_ADDIH_A = 0x11,
OPC1_32_RLC_MFCR = 0x4d,
OPC1_32_RLC_MOV = 0x3b,
+ OPC1_32_RLC_MOV_64 = 0xfb, /* 1.6 only */
OPC1_32_RLC_MOV_U = 0xbb,
OPC1_32_RLC_MOV_H = 0x7b,
OPC1_32_RLC_MOVH_A = 0x91,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [Qemu-devel] [PATCH 3/4] target-tricore: add missing 64-bit MOV in RLC format
2014-12-12 14:10 ` [Qemu-devel] [PATCH 3/4] target-tricore: add missing 64-bit MOV in RLC format Alex Zuepke
@ 2014-12-12 16:30 ` Bastian Koppelmann
0 siblings, 0 replies; 8+ messages in thread
From: Bastian Koppelmann @ 2014-12-12 16:30 UTC (permalink / raw)
To: Alex Zuepke, qemu-devel
On 12/12/2014 02:10 PM, Alex Zuepke wrote:
> Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de>
> ---
> target-tricore/translate.c | 12 ++++++++++++
> target-tricore/tricore-opcodes.h | 1 +
> 2 files changed, 13 insertions(+)
>
> diff --git a/target-tricore/translate.c b/target-tricore/translate.c
> index c132223..e3eeedb 100644
> --- a/target-tricore/translate.c
> +++ b/target-tricore/translate.c
> @@ -3781,6 +3781,17 @@ static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx,
> case OPC1_32_RLC_MOV:
> tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
> break;
> + case OPC1_32_RLC_MOV_64:
> + if (tricore_feature(env, TRICORE_FEATURE_16)) {
> + if ((r2 & 0x1) != 0) {
> + /* TODO: raise OPD trap */
> + }
This reminds me, that there should be a mechanism, which can create
traps for all instructions that use two 32bit regs as one 64bit one.
> + tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
> + tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15);
> + } else {
> + /* TODO: raise illegal opcode trap */
> + }
> + break;
> case OPC1_32_RLC_MOV_U:
> const16 = MASK_OP_RLC_CONST16(ctx->opcode);
> tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
> @@ -4021,6 +4032,7 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
> case OPC1_32_RLC_ADDIH_A:
> case OPC1_32_RLC_MFCR:
> case OPC1_32_RLC_MOV:
> + case OPC1_32_RLC_MOV_64:
> case OPC1_32_RLC_MOV_U:
> case OPC1_32_RLC_MOV_H:
> case OPC1_32_RLC_MOVH_A:
> diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
> index 7aa6aed..a76a7e4 100644
> --- a/target-tricore/tricore-opcodes.h
> +++ b/target-tricore/tricore-opcodes.h
> @@ -487,6 +487,7 @@ enum {
> OPC1_32_RLC_ADDIH_A = 0x11,
> OPC1_32_RLC_MFCR = 0x4d,
> OPC1_32_RLC_MOV = 0x3b,
> + OPC1_32_RLC_MOV_64 = 0xfb, /* 1.6 only */
> OPC1_32_RLC_MOV_U = 0xbb,
> OPC1_32_RLC_MOV_H = 0x7b,
> OPC1_32_RLC_MOVH_A = 0x91,
Looks good to me anyway.
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Qemu-devel] [PATCH 4/4] target-tricore: pretty-print register dump and show more status registers
[not found] <1418393430-12336-1-git-send-email-alexander.zuepke@hs-rm.de>
` (2 preceding siblings ...)
2014-12-12 14:10 ` [Qemu-devel] [PATCH 3/4] target-tricore: add missing 64-bit MOV in RLC format Alex Zuepke
@ 2014-12-12 14:10 ` Alex Zuepke
2014-12-12 16:35 ` Bastian Koppelmann
3 siblings, 1 reply; 8+ messages in thread
From: Alex Zuepke @ 2014-12-12 14:10 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, Alex Zuepke
Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de>
---
target-tricore/translate.c | 16 +++++++++++-----
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index e3eeedb..d1b845b 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -87,19 +87,25 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f,
CPUTriCoreState *env = &cpu->env;
int i;
- cpu_fprintf(f, "PC=%08x\n", env->PC);
+ cpu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC);
+ cpu_fprintf(f, " PCXI: " TARGET_FMT_lx, env->PCXI);
+ cpu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX);
+ cpu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX);
+ cpu_fprintf(f, " PSW: " TARGET_FMT_lx, env->PSW);
+
for (i = 0; i < 16; ++i) {
if ((i & 3) == 0) {
- cpu_fprintf(f, "GPR A%02d:", i);
+ cpu_fprintf(f, "\nGPR A%02d:", i);
}
- cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames_a[i], env->gpr_a[i]);
+ cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]);
}
for (i = 0; i < 16; ++i) {
if ((i & 3) == 0) {
- cpu_fprintf(f, "GPR D%02d:", i);
+ cpu_fprintf(f, "\nGPR D%02d:", i);
}
- cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames_d[i], env->gpr_d[i]);
+ cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]);
}
+ cpu_fprintf(f, "\n");
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [Qemu-devel] [PATCH 4/4] target-tricore: pretty-print register dump and show more status registers
2014-12-12 14:10 ` [Qemu-devel] [PATCH 4/4] target-tricore: pretty-print register dump and show more status registers Alex Zuepke
@ 2014-12-12 16:35 ` Bastian Koppelmann
0 siblings, 0 replies; 8+ messages in thread
From: Bastian Koppelmann @ 2014-12-12 16:35 UTC (permalink / raw)
To: Alex Zuepke, qemu-devel
On 12/12/2014 02:10 PM, Alex Zuepke wrote:
> Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de>
> ---
> target-tricore/translate.c | 16 +++++++++++-----
> 1 file changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/target-tricore/translate.c b/target-tricore/translate.c
> index e3eeedb..d1b845b 100644
> --- a/target-tricore/translate.c
> +++ b/target-tricore/translate.c
> @@ -87,19 +87,25 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f,
> CPUTriCoreState *env = &cpu->env;
> int i;
>
> - cpu_fprintf(f, "PC=%08x\n", env->PC);
> + cpu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC);
> + cpu_fprintf(f, " PCXI: " TARGET_FMT_lx, env->PCXI);
> + cpu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX);
> + cpu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX);
> + cpu_fprintf(f, " PSW: " TARGET_FMT_lx, env->PSW);
I'm afraid that won't work, since the user status bits of the PSW are
cached for faster access. Consider using psw_read().
> +
> for (i = 0; i < 16; ++i) {
> if ((i & 3) == 0) {
> - cpu_fprintf(f, "GPR A%02d:", i);
> + cpu_fprintf(f, "\nGPR A%02d:", i);
> }
> - cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames_a[i], env->gpr_a[i]);
> + cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]);
> }
> for (i = 0; i < 16; ++i) {
> if ((i & 3) == 0) {
> - cpu_fprintf(f, "GPR D%02d:", i);
> + cpu_fprintf(f, "\nGPR D%02d:", i);
> }
> - cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames_d[i], env->gpr_d[i]);
> + cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]);
> }
> + cpu_fprintf(f, "\n");
>
> }
>
Cheers,
Bastian
^ permalink raw reply [flat|nested] 8+ messages in thread