From: Richard Henderson <rth@twiddle.net>
To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 3/8] target-tricore: Add instructions of RR opcode format, that have 0xf as the first opcode
Date: Fri, 12 Dec 2014 12:04:38 -0800 [thread overview]
Message-ID: <548B4A56.3050906@twiddle.net> (raw)
In-Reply-To: <1418405504-11175-4-git-send-email-kbastian@mail.uni-paderborn.de>
On 12/12/2014 09:31 AM, Bastian Koppelmann wrote:
> +DEF_HELPER_1(clo, i32, i32)
> +DEF_HELPER_1(clo_h, i32, i32)
> +DEF_HELPER_1(clz, i32, i32)
> +DEF_HELPER_1(clz_h, i32, i32)
> +DEF_HELPER_1(cls, i32, i32)
> +DEF_HELPER_1(cls_h, i32, i32)
> +/* sh */
> +DEF_HELPER_2(sh, i32, i32, i32)
> +DEF_HELPER_2(sh_h, i32, i32, i32)
I don't think it's come up so far, since most of your helpers have been
complex, and have been modifying PSW bits. But you should annotate these with
DEF_HELPER_FLAGS so that TCG knows that there are no side effects.
I do wonder about expanding helper_sh inline, but we can do that later.
r~
next prev parent reply other threads:[~2014-12-12 20:05 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-12 17:31 [Qemu-devel] [PATCH 0/8] TriCore add instructions of RR and RR1 opcode format Bastian Koppelmann
2014-12-12 17:31 ` [Qemu-devel] [PATCH 1/8] target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32 Bastian Koppelmann
2014-12-12 19:31 ` Richard Henderson
2014-12-12 17:31 ` [Qemu-devel] [PATCH 2/8] target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode Bastian Koppelmann
2014-12-12 19:49 ` Richard Henderson
2014-12-12 17:31 ` [Qemu-devel] [PATCH 3/8] target-tricore: Add instructions of RR opcode format, that have 0xf " Bastian Koppelmann
2014-12-12 20:04 ` Richard Henderson [this message]
2014-12-12 17:31 ` [Qemu-devel] [PATCH 4/8] target-tricore: Add instructions of RR opcode format, that have 0x1 " Bastian Koppelmann
2014-12-12 20:06 ` Richard Henderson
2014-12-12 17:31 ` [Qemu-devel] [PATCH 5/8] target-tricore: Add instructions of RR opcode format, that have 0x4b " Bastian Koppelmann
2014-12-12 20:45 ` Richard Henderson
2014-12-17 15:43 ` Bastian Koppelmann
2014-12-12 17:31 ` [Qemu-devel] [PATCH 6/8] target-tricore: Add missing 1.6 insn of BOL opcode format Bastian Koppelmann
2014-12-12 20:46 ` Richard Henderson
2014-12-12 17:31 ` [Qemu-devel] [PATCH 7/8] target-tricore: Fix MFCR/MTCR insn and B format offset Bastian Koppelmann
2014-12-12 20:49 ` Richard Henderson
2014-12-12 17:31 ` [Qemu-devel] [PATCH 8/8] target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode Bastian Koppelmann
2014-12-12 20:53 ` Richard Henderson
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