From: Richard Henderson <rth@twiddle.net>
To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 8/8] target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode
Date: Fri, 12 Dec 2014 12:53:52 -0800 [thread overview]
Message-ID: <548B55E0.2020803@twiddle.net> (raw)
In-Reply-To: <1418405504-11175-9-git-send-email-kbastian@mail.uni-paderborn.de>
On 12/12/2014 09:31 AM, Bastian Koppelmann wrote:
> +#define MUL_H_OP(ARG00, ARG01, ARG10, ARG11) \
> +uint64_t helper_mulh_##ARG00 ##_##ARG01 ##_##ARG10 ##_##ARG11( \
> + CPUTriCoreState *env, target_ulong arg1, target_ulong arg2, \
> + target_ulong n) \
> +{ \
> + uint64_t ret; \
> + uint32_t result0, result1; \
> + int32_t arg00 = sextract32(arg1, ARG00, 16); \
> + int32_t arg01 = sextract32(arg1, ARG01, 16); \
> + int32_t arg10 = sextract32(arg2, ARG10, 16); \
> + int32_t arg11 = sextract32(arg2, ARG11, 16); \
Since these functions only differ in the extraction of the arguments,
it'd probably be better to only have 3 helpers instead of 12 and do
this extraction in tcg as part of the call.
r~
prev parent reply other threads:[~2014-12-12 20:54 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-12 17:31 [Qemu-devel] [PATCH 0/8] TriCore add instructions of RR and RR1 opcode format Bastian Koppelmann
2014-12-12 17:31 ` [Qemu-devel] [PATCH 1/8] target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32 Bastian Koppelmann
2014-12-12 19:31 ` Richard Henderson
2014-12-12 17:31 ` [Qemu-devel] [PATCH 2/8] target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode Bastian Koppelmann
2014-12-12 19:49 ` Richard Henderson
2014-12-12 17:31 ` [Qemu-devel] [PATCH 3/8] target-tricore: Add instructions of RR opcode format, that have 0xf " Bastian Koppelmann
2014-12-12 20:04 ` Richard Henderson
2014-12-12 17:31 ` [Qemu-devel] [PATCH 4/8] target-tricore: Add instructions of RR opcode format, that have 0x1 " Bastian Koppelmann
2014-12-12 20:06 ` Richard Henderson
2014-12-12 17:31 ` [Qemu-devel] [PATCH 5/8] target-tricore: Add instructions of RR opcode format, that have 0x4b " Bastian Koppelmann
2014-12-12 20:45 ` Richard Henderson
2014-12-17 15:43 ` Bastian Koppelmann
2014-12-12 17:31 ` [Qemu-devel] [PATCH 6/8] target-tricore: Add missing 1.6 insn of BOL opcode format Bastian Koppelmann
2014-12-12 20:46 ` Richard Henderson
2014-12-12 17:31 ` [Qemu-devel] [PATCH 7/8] target-tricore: Fix MFCR/MTCR insn and B format offset Bastian Koppelmann
2014-12-12 20:49 ` Richard Henderson
2014-12-12 17:31 ` [Qemu-devel] [PATCH 8/8] target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode Bastian Koppelmann
2014-12-12 20:53 ` Richard Henderson [this message]
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