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Subject: Re: [Qemu-devel] [PATCH 8/8] target-tricore: Add instructions of
 RR1 opcode format, that have 0xb3 as first opcode
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To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, qemu-devel@nongnu.org

On 12/12/2014 09:31 AM, Bastian Koppelmann wrote:
> +#define MUL_H_OP(ARG00, ARG01, ARG10, ARG11)                                \
> +uint64_t helper_mulh_##ARG00 ##_##ARG01 ##_##ARG10 ##_##ARG11(              \
> +         CPUTriCoreState *env, target_ulong arg1, target_ulong arg2,        \
> +         target_ulong n)                                                    \
> +{                                                                           \
> +    uint64_t ret;                                                           \
> +    uint32_t result0, result1;                                              \
> +    int32_t arg00 = sextract32(arg1, ARG00, 16);                            \
> +    int32_t arg01 = sextract32(arg1, ARG01, 16);                            \
> +    int32_t arg10 = sextract32(arg2, ARG10, 16);                            \
> +    int32_t arg11 = sextract32(arg2, ARG11, 16);                            \

Since these functions only differ in the extraction of the arguments,
it'd probably be better to only have 3 helpers instead of 12 and do
this extraction in tcg as part of the call.



r~