From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42286) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XzYjE-0004dh-On for qemu-devel@nongnu.org; Fri, 12 Dec 2014 17:30:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XzYj4-00059O-0H for qemu-devel@nongnu.org; Fri, 12 Dec 2014 17:30:28 -0500 Received: from mail-pa0-f44.google.com ([209.85.220.44]:41222) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XzYj3-00059B-Qm for qemu-devel@nongnu.org; Fri, 12 Dec 2014 17:30:17 -0500 Received: by mail-pa0-f44.google.com with SMTP id et14so8061692pad.17 for ; Fri, 12 Dec 2014 14:30:16 -0800 (PST) Message-ID: <548B6C72.7020601@ozlabs.ru> Date: Sat, 13 Dec 2014 09:30:10 +1100 From: Alexey Kardashevskiy MIME-Version: 1.0 References: <1418377089-17331-1-git-send-email-aik@ozlabs.ru> In-Reply-To: <1418377089-17331-1-git-send-email-aik@ozlabs.ru> Content-Type: text/plain; charset=koi8-r Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2] spapr-pci: Enable huge BARs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Alexander Graf On 12/12/2014 08:38 PM, Alexey Kardashevskiy wrote: > At the moment sPAPR only supports 512MB window for MMIO BARs. However > modern devices might want bigger 64bit BARs. > > This extends MMIO window from 512MB to 62GB (aligned to > SPAPR_PCI_WINDOW_SPACING) and advertises it in 2 records in > the PHB's "ranges" property. 32bit has all the space from > SPAPR_PCI_MEM_WIN_BUS_OFFSET till the end of 4GB, 64bit has the rest > of the window. > > Suggested-by: Benjamin Herrenschmidt > Signed-off-by: Alexey Kardashevskiy > --- > Changes: > v2: > * do not change existing memory layout > * do not create another mmio window > --- > hw/ppc/spapr_pci.c | 8 +++++++- > include/hw/pci-host/spapr.h | 7 ++++--- > 2 files changed, 11 insertions(+), 4 deletions(-) > > diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c > index 21b95b3..3641f87 100644 > --- a/hw/ppc/spapr_pci.c > +++ b/hw/ppc/spapr_pci.c > @@ -862,6 +862,7 @@ int spapr_populate_pci_dt(sPAPRPHBState *phb, > int bus_off, i, j; > char nodename[256]; > uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; > + const uint32_t win32size = (1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET; > struct { > uint32_t hi; > uint64_t child; > @@ -876,7 +877,12 @@ int spapr_populate_pci_dt(sPAPRPHBState *phb, > { > cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), > cpu_to_be64(phb->mem_win_addr), > - cpu_to_be64(memory_region_size(&phb->memwindow)), > + cpu_to_be64(win32size), > + }, > + { > + cpu_to_be32(b_ss(3)), cpu_to_be64(1ULL << 32), > + cpu_to_be64(phb->mem_win_addr + win32size), > + cpu_to_be64(memory_region_size(&phb->memwindow) - win32size) > }, > }; > uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; > diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h > index 4ea2a0d..dc0d870 100644 > --- a/include/hw/pci-host/spapr.h > +++ b/include/hw/pci-host/spapr.h > @@ -96,17 +96,18 @@ struct sPAPRPHBVFIOState { > > #define SPAPR_PCI_BASE_BUID 0x800000020000000ULL > > +#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL > + > #define SPAPR_PCI_WINDOW_BASE 0x10000000000ULL > #define SPAPR_PCI_WINDOW_SPACING 0x1000000000ULL > #define SPAPR_PCI_MMIO_WIN_OFF 0xA0000000 > -#define SPAPR_PCI_MMIO_WIN_SIZE 0x20000000 > +#define SPAPR_PCI_MMIO_WIN_SIZE (0x1000000000ULL - \ > + SPAPR_PCI_MEM_WIN_BUS_OFFSET) Uff, should have been: +#define SPAPR_PCI_MMIO_WIN_SIZE (SPAPR_PCI_WINDOW_SPACING - \ + SPAPR_PCI_MEM_WIN_BUS_OFFSET) > #define SPAPR_PCI_IO_WIN_OFF 0x80000000 > #define SPAPR_PCI_IO_WIN_SIZE 0x10000 > > #define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL > > -#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL > - > static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin) > { > return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq); > -- Alexey