From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>, Ake Koomsin <ake@igel.co.jp>
Cc: qemu-devel@nongnu.org, "open list:ARM TCG CPUs" <qemu-arm@nongnu.org>
Subject: Re: [PATCH] target/arm: honor HCR_E2H for AT S1E2R and AT S1E2W address translation
Date: Wed, 26 Oct 2022 09:50:01 +1000 [thread overview]
Message-ID: <548c9d6e-16d2-1a61-a1ba-ee4aded712a7@linaro.org> (raw)
In-Reply-To: <CAFEAcA_E5P2+ybnhH05DNsb_LuKjROU9-NKke46x+_LO7zr-qw@mail.gmail.com>
On 10/25/22 22:25, Peter Maydell wrote:
> In the pseudocode, E2H is handled by changing the behaviour not
> just of the S1E2 ops, but also of the S1E1 ops. If E2H is set:
> * the S1E2 ops use the EL2&0 regime, but continue to ignore
> PSTATE.PAN
> * the S1E1 ops also use the EL2&0 regime, with the S1E1RP and
> S1E1WP ops looking at PSTATE.PAN and the others not
>
> Richard -- do we want to just do the same thing, or do
> our MMUIdx uses differ from the architectural translation
> regimes in a way that means we need to do something else?
We want to do the same thing. The *_PAN MMUIdx are intended to be exactly like the
architecture, when PAN is enabled and not ignored.
r~
next prev parent reply other threads:[~2022-10-25 23:51 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-17 9:30 [PATCH] target/arm: honor HCR_E2H for AT S1E2R and AT S1E2W address translation Ake Koomsin
2022-10-25 12:25 ` Peter Maydell
2022-10-25 23:50 ` Richard Henderson [this message]
2022-10-26 4:27 ` ake
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