From: Richard Henderson <rth@twiddle.net>
To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v2 1/8] target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32
Date: Wed, 17 Dec 2014 09:42:28 -0600 [thread overview]
Message-ID: <5491A464.3010106@twiddle.net> (raw)
In-Reply-To: <1418831961-27658-2-git-send-email-kbastian@mail.uni-paderborn.de>
On 12/17/2014 09:59 AM, Bastian Koppelmann wrote:
> Those makros are exclusively used for 32 bit arithmetics and won't work for
> 16 bit with two halfwords. So lets get rid of the len parameter and make them
> always use 32 bit. Now no token pasting is needed anymore and they can be
> regular functions.
>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> ---
> v1 -> v2:
> - SSOV32/SUOV32 are now regular functions.
>
> target-tricore/op_helper.c | 134 ++++++++++++++++++++-------------------------
> 1 file changed, 58 insertions(+), 76 deletions(-)
Reviewed-by: Richard Henderson <rth@twiddle.net>
r~
next prev parent reply other threads:[~2014-12-17 15:42 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-17 15:59 [Qemu-devel] [PATCH v2 0/8] TriCore add instructions of RR and RR1 opcode format Bastian Koppelmann
2014-12-17 15:59 ` [Qemu-devel] [PATCH v2 1/8] target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32 Bastian Koppelmann
2014-12-17 15:42 ` Richard Henderson [this message]
2014-12-17 15:59 ` [Qemu-devel] [PATCH v2 2/8] target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode Bastian Koppelmann
2014-12-17 15:47 ` Richard Henderson
2014-12-17 15:59 ` [Qemu-devel] [PATCH v2 3/8] target-tricore: Add instructions of RR opcode format, that have 0xf " Bastian Koppelmann
2014-12-17 15:48 ` Richard Henderson
2014-12-17 15:59 ` [Qemu-devel] [PATCH v2 4/8] target-tricore: Add instructions of RR opcode format, that have 0x1 " Bastian Koppelmann
2014-12-17 15:59 ` [Qemu-devel] [PATCH v2 5/8] target-tricore: Add instructions of RR opcode format, that have 0x4b " Bastian Koppelmann
2014-12-17 15:51 ` Richard Henderson
2014-12-17 15:59 ` [Qemu-devel] [PATCH v2 6/8] target-tricore: Add missing 1.6 insn of BOL opcode format Bastian Koppelmann
2014-12-17 15:59 ` [Qemu-devel] [PATCH v2 7/8] target-tricore: Fix MFCR/MTCR insn and B format offset Bastian Koppelmann
2014-12-17 15:59 ` [Qemu-devel] [PATCH v2 8/8] target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode Bastian Koppelmann
2014-12-17 16:08 ` Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=5491A464.3010106@twiddle.net \
--to=rth@twiddle.net \
--cc=kbastian@mail.uni-paderborn.de \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).