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From: Richard Henderson <rth@twiddle.net>
To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v2 2/8] target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode
Date: Wed, 17 Dec 2014 09:47:06 -0600	[thread overview]
Message-ID: <5491A57A.20707@twiddle.net> (raw)
In-Reply-To: <1418831961-27658-3-git-send-email-kbastian@mail.uni-paderborn.de>

On 12/17/2014 09:59 AM, Bastian Koppelmann wrote:
> Add instructions of RR opcode format, that have 0xb as the first opcode.
> Add helper functions, for hword and byte arithmetics:
>     * add_h_ssov/suov: Add two halfword and saturate on overflow.
>     * sub_h_ssov/suov: Sub two halfword and saturate on overflow.
>     * absdif_h_ssov: Compute absolute difference for halfwords and saturate on overflow.
>     * abs_h_ssov/suov: Compute absolute value for two halfwords and saturate on overflow.
>     * abs_b/h: Compute absolute value for four/two bytes/halfwords
>     * absdif_b/h: Compute absolute difference for four/two bytes/halfwords
>     * add_b/h: Add four/two bytes/halfwords.
>     * sub_b/h: Sub four/two bytes/halfwords.
>     * eq_b/h: Compare four/two bytes/halfwords with four/two bytes/halfwords on
>               equality and set all bits of to either one ore zero.
>     * eqany_b/h: Compare four/two bytes/halfwords with four/two bytes/halfwords on equality.
>     * lt_b/bu/h/hu: Compare four/two bytes/halfwords with four/two bytes/halfwords
>                     on less than signed and unsigned.
>     * max_b/bu/h/hu: Calculate max for four/two bytes/halfwords signed and unsigned.
>     * min_b/bu/h/hu: Calculate min for four/two bytes/halfwords signed and unsigned.
> Add helper function abs_ssov, that computes the absolute value for a 32 bit integer and saturates on overflow.
> Add microcode generator functions:
>     * gen_sub_CC: Caluclates sub and sets the carry bit.
>     * gen_subc_CC: Caluclates sub and carry and sets the carry bit
>     * gen_abs: Compute absolute value for a 32 bit integer.
>     * gen_cond_w: Compares two 32 bit values on cond and sets result either zero or all bits one.
> 
> OPC2_32_RR_MIN switched with OPC2_32_RR_MIN_U.
> 
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> ---
> v1 -> v2:
>     - gen_cond_w now uses neg and saves a temp.
>     - SSOV16/SUOV16 are now regular functions.
>     - Use TCG_CALL_NO_RWG_SE for all helpers not using globals.

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~

  reply	other threads:[~2014-12-17 15:47 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-12-17 15:59 [Qemu-devel] [PATCH v2 0/8] TriCore add instructions of RR and RR1 opcode format Bastian Koppelmann
2014-12-17 15:59 ` [Qemu-devel] [PATCH v2 1/8] target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32 Bastian Koppelmann
2014-12-17 15:42   ` Richard Henderson
2014-12-17 15:59 ` [Qemu-devel] [PATCH v2 2/8] target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode Bastian Koppelmann
2014-12-17 15:47   ` Richard Henderson [this message]
2014-12-17 15:59 ` [Qemu-devel] [PATCH v2 3/8] target-tricore: Add instructions of RR opcode format, that have 0xf " Bastian Koppelmann
2014-12-17 15:48   ` Richard Henderson
2014-12-17 15:59 ` [Qemu-devel] [PATCH v2 4/8] target-tricore: Add instructions of RR opcode format, that have 0x1 " Bastian Koppelmann
2014-12-17 15:59 ` [Qemu-devel] [PATCH v2 5/8] target-tricore: Add instructions of RR opcode format, that have 0x4b " Bastian Koppelmann
2014-12-17 15:51   ` Richard Henderson
2014-12-17 15:59 ` [Qemu-devel] [PATCH v2 6/8] target-tricore: Add missing 1.6 insn of BOL opcode format Bastian Koppelmann
2014-12-17 15:59 ` [Qemu-devel] [PATCH v2 7/8] target-tricore: Fix MFCR/MTCR insn and B format offset Bastian Koppelmann
2014-12-17 15:59 ` [Qemu-devel] [PATCH v2 8/8] target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode Bastian Koppelmann
2014-12-17 16:08   ` Richard Henderson

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