From: Alexander Graf <agraf@suse.de>
To: Tom Musta <tommusta@gmail.com>,
qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 0/9] target-ppc: Rudimentary Support for Transactional Memory
Date: Thu, 18 Dec 2014 23:52:16 +0100 [thread overview]
Message-ID: <54935AA0.2030406@suse.de> (raw)
In-Reply-To: <1418920477-11669-1-git-send-email-tommusta@gmail.com>
On 18.12.14 17:34, Tom Musta wrote:
> This patch series introduces rudimentary support for the Transactional Memory
> (TM) feature of Power ISA V2.07. In a nutshell, software uses the feature by
> initiating a transaction via the tbegin instruction. Hardware then accumulates
> storage accesses until the transaction is committed via the tend instruction).
> At this point, either the instruction completes and all storage accesses are
> atomic with respect to other processors; or the transaction fails and processor
> state reverts to the point of tbegin. Transaction success or failure is recorded
> in CR[0] and the instruction immediately following tbegin is expected to inspect
> this field and provide an error path to properly handle failure.
>
> Accurately emulating such a feature in QEMU is quite difficult. Instead, the
> approach taken here simply fails the transaction at the point of tbegin and
> thus immediately takes software down the error handlling path. As such, this can
> be considered a toleration mode for any software that utilizes the TM feature.
> Valgrind has taken a similar approach. There are no immediate plans to implement
> a more sophisticated model.
>
> Currently, Power8 is the only Power processor that supports TM.
Thanks, applied all to ppc-next.
Alex
prev parent reply other threads:[~2014-12-18 22:52 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-18 16:34 [Qemu-devel] [PATCH 0/9] target-ppc: Rudimentary Support for Transactional Memory Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 1/9] target-ppc: Introduce Instruction Type " Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 2/9] target-ppc: Introduce Feature Flag " Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 3/9] target-ppc: Introduce tm_enabled Bit to CPU State Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 4/9] target-ppc: Power8 Supports Transactional Memory Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 5/9] target-ppc: Introduce TEXASRU Bit Fields Tom Musta
2014-12-18 17:02 ` Alexander Graf
2014-12-18 18:10 ` Tom Musta
2014-12-18 18:29 ` Alexander Graf
2014-12-18 18:41 ` Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 6/9] target-ppc: Introduce tbegin Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 7/9] target-ppc: Introduce TM Noops Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 8/9] target-ppc: Introduce tcheck Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 9/9] target-ppc: Introduce Privileged TM Noops Tom Musta
2014-12-19 10:20 ` Fam Zheng
2014-12-20 21:22 ` Tom Musta
2014-12-18 22:52 ` Alexander Graf [this message]
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