From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57006) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y1jvl-0003gv-Fs for qemu-devel@nongnu.org; Thu, 18 Dec 2014 17:52:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Y1jve-0002FP-0N for qemu-devel@nongnu.org; Thu, 18 Dec 2014 17:52:25 -0500 Message-ID: <54935AA0.2030406@suse.de> Date: Thu, 18 Dec 2014 23:52:16 +0100 From: Alexander Graf MIME-Version: 1.0 References: <1418920477-11669-1-git-send-email-tommusta@gmail.com> In-Reply-To: <1418920477-11669-1-git-send-email-tommusta@gmail.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 0/9] target-ppc: Rudimentary Support for Transactional Memory List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Tom Musta , qemu-devel@nongnu.org, qemu-ppc@nongnu.org On 18.12.14 17:34, Tom Musta wrote: > This patch series introduces rudimentary support for the Transactional Memory > (TM) feature of Power ISA V2.07. In a nutshell, software uses the feature by > initiating a transaction via the tbegin instruction. Hardware then accumulates > storage accesses until the transaction is committed via the tend instruction). > At this point, either the instruction completes and all storage accesses are > atomic with respect to other processors; or the transaction fails and processor > state reverts to the point of tbegin. Transaction success or failure is recorded > in CR[0] and the instruction immediately following tbegin is expected to inspect > this field and provide an error path to properly handle failure. > > Accurately emulating such a feature in QEMU is quite difficult. Instead, the > approach taken here simply fails the transaction at the point of tbegin and > thus immediately takes software down the error handlling path. As such, this can > be considered a toleration mode for any software that utilizes the TM feature. > Valgrind has taken a similar approach. There are no immediate plans to implement > a more sophisticated model. > > Currently, Power8 is the only Power processor that supports TM. Thanks, applied all to ppc-next. Alex