From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56125) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y21Mc-0004Ba-Fd for qemu-devel@nongnu.org; Fri, 19 Dec 2014 12:29:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Y21MX-0006fW-5Q for qemu-devel@nongnu.org; Fri, 19 Dec 2014 12:29:18 -0500 Message-ID: <54946067.5060401@suse.de> Date: Fri, 19 Dec 2014 18:29:11 +0100 From: Alexander Graf MIME-Version: 1.0 References: In-Reply-To: Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] PPC: e500: Fix GPIO controller interrupt number List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Amit Tomar , "qemu-devel@nongnu.org" , "qemu-ppc@nongnu.org" On 19.12.14 15:20, Amit Tomar wrote: > This patch sets the GPIO controller interrupt number to 47,not 43 (and the Device tree agrees). > > > Signed-off-by: Amit Singh Tomar Thanks, applied to ppc-next with modified commit message. Let's try to improve the patch description next time ;). Alex Subject: [PATCH] PPC: e500: Fix GPIO controller interrupt number The GPIO controller lives at IRQ 47, not 43 on real hardware. This is a problem because IRQ 43 is occupied by the I2C controller which we want to implement next, so we'd have a conflict on that IRQ number. Move the GPIO controller to IRQ 47 where it belongs. Signed-off-by: Amit Singh Tomar Signed-off-by: Alexander Graf