From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48981) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YDFqs-0004gw-QZ for qemu-devel@nongnu.org; Mon, 19 Jan 2015 12:11:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YDFqp-0007bh-Gf for qemu-devel@nongnu.org; Mon, 19 Jan 2015 12:10:58 -0500 Received: from mail-we0-x232.google.com ([2a00:1450:400c:c03::232]:61663) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YDFqp-0007bW-6e for qemu-devel@nongnu.org; Mon, 19 Jan 2015 12:10:55 -0500 Received: by mail-we0-f178.google.com with SMTP id p10so32561162wes.9 for ; Mon, 19 Jan 2015 09:10:54 -0800 (PST) Sender: Paolo Bonzini Message-ID: <54BD3A9B.1090608@redhat.com> Date: Mon, 19 Jan 2015 18:10:51 +0100 From: Paolo Bonzini MIME-Version: 1.0 References: <1421120079-987-1-git-send-email-jsnow@redhat.com> <1421120079-987-14-git-send-email-jsnow@redhat.com> In-Reply-To: <1421120079-987-14-git-send-email-jsnow@redhat.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 13/14] qtest/ahci: Bookmark FB and CLB pointers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: John Snow , qemu-devel@nongnu.org Cc: kwolf@redhat.com, marc.mari.barcelo@gmail.com, armbru@redhat.com, stefanha@redhat.com, mreitz@redhat.com On 13/01/2015 04:34, John Snow wrote: > Instead of re-querying the AHCI device for the FB and CLB buffers, save > the pointer we gave to the device during initialization and reference > these values instead. > > Signed-off-by: John Snow > --- > tests/ahci-test.c | 42 ++++++++++++++++++++---------------------- > tests/libqos/ahci.h | 6 ++++++ > 2 files changed, 26 insertions(+), 22 deletions(-) > > diff --git a/tests/ahci-test.c b/tests/ahci-test.c > index 0bf572e..4a723c0 100644 > --- a/tests/ahci-test.c > +++ b/tests/ahci-test.c > @@ -206,7 +206,7 @@ static void ahci_hba_enable(AHCIQState *ahci) > * PxCMD.FR "FIS Receive Running" > * PxCMD.CR "Command List Running" > */ > - uint32_t reg, ports_impl, clb, fb; > + uint32_t reg, ports_impl; > uint16_t i; > uint8_t num_cmd_slots; > > @@ -255,16 +255,20 @@ static void ahci_hba_enable(AHCIQState *ahci) > > /* Allocate Memory for the Command List Buffer & FIS Buffer */ > /* PxCLB space ... 0x20 per command, as in 4.2.2 p 36 */ > - clb = ahci_alloc(ahci, num_cmd_slots * 0x20); > - g_test_message("CLB: 0x%08x", clb); > - ahci_px_wreg(ahci, i, AHCI_PX_CLB, clb); > - g_assert_cmphex(clb, ==, ahci_px_rreg(ahci, i, AHCI_PX_CLB)); > + ahci->port[i].clb = ahci_alloc(ahci, num_cmd_slots * 0x20); > + qmemset(ahci->port[i].clb, 0x00, 0x100); > + g_test_message("CLB: 0x%08lx", ahci->port[i].clb); > + ahci_px_wreg(ahci, i, AHCI_PX_CLB, ahci->port[i].clb); > + g_assert_cmphex(ahci->port[i].clb, ==, > + ahci_px_rreg(ahci, i, AHCI_PX_CLB)); > > /* PxFB space ... 0x100, as in 4.2.1 p 35 */ > - fb = ahci_alloc(ahci, 0x100); > - g_test_message("FB: 0x%08x", fb); > - ahci_px_wreg(ahci, i, AHCI_PX_FB, fb); > - g_assert_cmphex(fb, ==, ahci_px_rreg(ahci, i, AHCI_PX_FB)); > + ahci->port[i].fb = ahci_alloc(ahci, 0x100); > + qmemset(ahci->port[i].fb, 0x00, 0x100); > + g_test_message("FB: 0x%08lx", ahci->port[i].fb); > + ahci_px_wreg(ahci, i, AHCI_PX_FB, ahci->port[i].fb); > + g_assert_cmphex(ahci->port[i].fb, ==, > + ahci_px_rreg(ahci, i, AHCI_PX_FB)); > > /* Clear PxSERR, PxIS, then IS.IPS[x] by writing '1's. */ > ahci_px_wreg(ahci, i, AHCI_PX_SERR, 0xFFFFFFFF); > @@ -883,7 +887,7 @@ static void ahci_test_identify(AHCIQState *ahci) > RegH2DFIS fis; > AHCICommand cmd; > PRD prd; > - uint32_t ports, reg, clb, table, fb, data_ptr; > + uint32_t ports, reg, table, data_ptr; > uint16_t buff[256]; > unsigned i; > int rc; > @@ -929,9 +933,7 @@ static void ahci_test_identify(AHCIQState *ahci) > g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_IS), ==, 0); > > /* Wipe the FIS-Recieve Buffer */ > - fb = ahci_px_rreg(ahci, i, AHCI_PX_FB); > - g_assert_cmphex(fb, !=, 0); > - qmemset(fb, 0x00, 0x100); > + qmemset(ahci->port[i].fb, 0x00, 0x100); > > /* Create a Command Table buffer. 0x80 is the smallest with a PRDTL of 0. */ > /* We need at least one PRD, so round up to the nearest 0x80 multiple. */ > @@ -943,13 +945,9 @@ static void ahci_test_identify(AHCIQState *ahci) > data_ptr = ahci_alloc(ahci, 512); > g_assert(data_ptr); > > - /* Grab the Command List Buffer pointer */ > - clb = ahci_px_rreg(ahci, i, AHCI_PX_CLB); > - g_assert(clb); > - > /* Copy the existing Command #0 structure from the CLB into local memory, > * and build a new command #0. */ > - memread(clb, &cmd, sizeof(cmd)); > + memread(ahci->port[i].clb, &cmd, sizeof(cmd)); > cmd.b1 = 5; /* reg_h2d_fis is 5 double-words long */ > cmd.b2 = 0x04; /* clear PxTFD.STS.BSY when done */ > cmd.prdtl = cpu_to_le16(1); /* One PRD table entry. */ > @@ -981,7 +979,7 @@ static void ahci_test_identify(AHCIQState *ahci) > memwrite(table + 0x80, &prd, sizeof(prd)); > > /* Commit Command #0, pointing to the Table, to the Command List Buffer. */ > - memwrite(clb, &cmd, sizeof(cmd)); > + memwrite(ahci->port[i].clb, &cmd, sizeof(cmd)); > > /* Everything is in place, but we haven't given the go-ahead yet. */ > g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_IS), ==, 0); > @@ -1012,12 +1010,12 @@ static void ahci_test_identify(AHCIQState *ahci) > ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR); > > /* Investigate CMD #0, assert that we read 512 bytes */ > - memread(clb, &cmd, sizeof(cmd)); > + memread(ahci->port[i].clb, &cmd, sizeof(cmd)); > g_assert_cmphex(512, ==, le32_to_cpu(cmd.prdbc)); > > /* Investigate FIS responses */ > - memread(fb + 0x20, pio, 0x20); > - memread(fb + 0x40, d2h, 0x20); > + memread(ahci->port[i].fb + 0x20, pio, 0x20); > + memread(ahci->port[i].fb + 0x40, d2h, 0x20); > g_assert_cmphex(pio->fis_type, ==, 0x5f); > g_assert_cmphex(d2h->fis_type, ==, 0x34); > g_assert_cmphex(pio->flags, ==, d2h->flags); > diff --git a/tests/libqos/ahci.h b/tests/libqos/ahci.h > index 56b1dfc..f4fc52b 100644 > --- a/tests/libqos/ahci.h > +++ b/tests/libqos/ahci.h > @@ -245,6 +245,11 @@ > > /*** Structures ***/ > > +typedef struct AHCIPortQState { > + uint64_t fb; > + uint64_t clb; > +} AHCIPortQState; > + > typedef struct AHCIQState { > QOSState *parent; > QPCIDevice *dev; > @@ -253,6 +258,7 @@ typedef struct AHCIQState { > uint32_t fingerprint; > uint32_t cap; > uint32_t cap2; > + AHCIPortQState port[32]; > } AHCIQState; > > /** > Reviewed-by: Paolo Bonzini