From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44100) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YDln0-0007xs-Lp for qemu-devel@nongnu.org; Tue, 20 Jan 2015 22:17:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YDlmx-00048K-Ej for qemu-devel@nongnu.org; Tue, 20 Jan 2015 22:17:06 -0500 Received: from mga09.intel.com ([134.134.136.24]:23086) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YDlmx-00047u-8k for qemu-devel@nongnu.org; Tue, 20 Jan 2015 22:17:03 -0500 Message-ID: <54BF1A27.2080006@intel.com> Date: Wed, 21 Jan 2015 11:16:55 +0800 From: "Chen, Tiejun" MIME-Version: 1.0 References: <1421659723-2496-1-git-send-email-tiejun.chen@intel.com> <1421659723-2496-9-git-send-email-tiejun.chen@intel.com> <20150120105827.GD26442@redhat.com> In-Reply-To: <20150120105827.GD26442@redhat.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [v6][PATCH 08/10] xen, gfx passthrough: support Intel IGD passthrough with VT-D List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" , allen.m.kay@intel.com Cc: yang.z.zhang@intel.com, pbonzini@redhat.com, qemu-devel@nongnu.org, aliguori@amazon.com, rth@twiddle.net >> +uint32_t xen_igd_pci_read(PCIDevice *pci_dev, uint32_t config_addr, int len) >> +{ >> + XenHostPCIDevice dev; >> + uint32_t val; >> + int r; >> + >> + /* IGD read/write is through the host bridge. >> + */ >> + assert(pci_dev->devfn == 0x00); >> + >> + if (!is_igd_passthrough(pci_dev)) { >> + goto read_default; >> + } >> + >> + /* Just work for the i915 driver. */ >> + switch (config_addr) { >> + case 0x08: /* revision id */ >> + case 0x2c: /* sybsystem vendor id */ >> + case 0x2e: /* sybsystem id */ >> + case 0x50: /* SNB: processor graphics control register */ >> + case 0x52: /* processor graphics control register */ >> + case 0xa0: /* top of memory */ > > Is this host physical memory? If yes how can using it in guest work? This is just a threshold value, not a start or end address :) > >> + case 0xa4: /* SNB: graphics base of stolen memory */ >> + case 0xa8: /* SNB: base of GTT stolen memory */ > > Same question for above two. I shouldn't matter since I remember we already discussed this previously but I can't sort out this from those emails now. Allen, Could you reexplain this? > >> + break; >> + default: >> + /* Just gets the emulated values. */ >> + goto read_default; >> + } >> + >> + /* Host read */ >> + r = xen_host_pci_device_get(&dev, 0, 0, 0, 0); >> + if (r) { >> + goto err_out; >> + } >> + >> + r = xen_host_pci_get_block(&dev, config_addr, (uint8_t *)&val, len); >> + if (r) { >> + goto err_out; >> + } >> + >> + xen_host_pci_device_put(&dev); >> + >> + return val; >> + >> +read_default: >> + return pci_default_read_config(pci_dev, config_addr, len); >> + >> +err_out: >> + XEN_PT_ERR(pci_dev, "Can't get pci_dev_host_bridge\n"); >> + return -1; >> +} > > Do any of the above registers change with time? Think about we just provide read ops, so they're not changed based on my experiential. > Does it work if we just read them when device is created > and put in dev->config? I think this is a good idea so I will go there and thank you. Tiejun