From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51974) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YE0Sp-0003f8-G2 for qemu-devel@nongnu.org; Wed, 21 Jan 2015 13:57:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YE0Sk-0003pP-HF for qemu-devel@nongnu.org; Wed, 21 Jan 2015 13:57:15 -0500 Received: from mail-qa0-x233.google.com ([2607:f8b0:400d:c00::233]:55755) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YE0Sk-0003pI-Di for qemu-devel@nongnu.org; Wed, 21 Jan 2015 13:57:10 -0500 Received: by mail-qa0-f51.google.com with SMTP id f12so33572704qad.10 for ; Wed, 21 Jan 2015 10:57:10 -0800 (PST) Sender: Richard Henderson Message-ID: <54BFF682.2080603@twiddle.net> Date: Wed, 21 Jan 2015 10:57:06 -0800 From: Richard Henderson MIME-Version: 1.0 References: <1421863489-7716-1-git-send-email-kbastian@mail.uni-paderborn.de> <1421863489-7716-4-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1421863489-7716-4-git-send-email-kbastian@mail.uni-paderborn.de> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 3/4] target-tricore: Add instructions of RRPW opcode format List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Bastian Koppelmann , qemu-devel@nongnu.org On 01/21/2015 10:04 AM, Bastian Koppelmann wrote: > Signed-off-by: Bastian Koppelmann > --- > target-tricore/translate.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 63 insertions(+) > > diff --git a/target-tricore/translate.c b/target-tricore/translate.c > index 4af31c2..73d8d7d 100644 > --- a/target-tricore/translate.c > +++ b/target-tricore/translate.c > @@ -5084,6 +5084,53 @@ static void decode_rr2_mul(CPUTriCoreState *env, DisasContext *ctx) > } > } > > +/* RRPW format */ > +static void decode_rrpw_extract_insert(CPUTriCoreState *env, DisasContext *ctx) > +{ > + uint32_t op2; > + int r1, r2, r3; > + int32_t pos, width; > + > + op2 = MASK_OP_RRPW_OP2(ctx->opcode); > + r1 = MASK_OP_RRPW_S1(ctx->opcode); > + r2 = MASK_OP_RRPW_S2(ctx->opcode); > + r3 = MASK_OP_RRPW_D(ctx->opcode); > + pos = MASK_OP_RRPW_POS(ctx->opcode); > + width = MASK_OP_RRPW_WIDTH(ctx->opcode); > + > + switch (op2) { > + case OPC2_32_RRPW_EXTR: > + if (pos + width <= 31) { > + tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos); > + tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32 - width)); > + /* sign extend it */ > + tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], (32 - width)); > + tcg_gen_sari_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], (32 - width)); You can do this with just the last two shifts: shl tmp, r3, 32 - pos - width sar r3, tmp, 32 - width Given that this appears to be the canonical way to sign-extend, you may well want to special case pos == 0, width == {8,16} to emit the tcg extension opcodes. > + temp = tcg_temp_new(); > + tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], const16); > + tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 32 - const16); > + tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); > + tcg_temp_free(temp); > + break; It should be worth special casing r1 == r2 as rotate left. r~