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Date: Wed, 28 Jan 2015 17:12:21 +0100
From: Claudio Fontana <claudio.fontana@huawei.com>
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Subject: Re: [Qemu-devel] [PATCH] FMULX should flushes operators to zero
 when FZ is set.
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To: Peter Maydell <peter.maydell@linaro.org>, =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>
Cc: Xiangyu Hu <libhu.so@gmail.com>, QEMU Developers <qemu-devel@nongnu.org>

Hi Peter,

On 28.01.2015 16:57, Peter Maydell wrote:
> On 28 January 2015 at 15:54, Alex Bennée <alex.bennee@linaro.org> wrote:
>> Do we have test cases that trip up here? It would be nice to include
>> them in our testing as the random nature of RISU has obviously failed to
>> trip up on this instruction.
> 
> Risu would probably catch this if we generated and ran test cases
> which set the FPSCR bits to something other than the default.
> (At least the 32-bit risugen lets you do this; I forget whether
> we wired up that bit in the 64-bit support code.)
> 
> -- PMM
> 

If nobody improved it from my implementation, the risugen script
will generate code which sets FPSR always unconditionally to 0,
while the FPCR is wired up with the user-provided "fpscr" option.
Not that there's any good reason behind it, probably both should be configurable..

Ciao,

Claudio