From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50541) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YJY5l-000425-9o for qemu-devel@nongnu.org; Thu, 05 Feb 2015 20:52:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YJY5i-0002Eu-2Q for qemu-devel@nongnu.org; Thu, 05 Feb 2015 20:52:21 -0500 Received: from mail-pd0-f177.google.com ([209.85.192.177]:46530) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YJY5h-0002En-Sj for qemu-devel@nongnu.org; Thu, 05 Feb 2015 20:52:17 -0500 Received: by pdjz10 with SMTP id z10so11388749pdj.13 for ; Thu, 05 Feb 2015 17:52:17 -0800 (PST) Sender: Richard Henderson Message-ID: <54D41E4D.6030603@twiddle.net> Date: Thu, 05 Feb 2015 17:52:13 -0800 From: Richard Henderson MIME-Version: 1.0 References: In-Reply-To: Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] Intel X86 hardware transactional memory List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Patrick Williams III , Xin Tong Cc: QEMU Developers On 02/04/2015 09:09 PM, Patrick Williams III wrote: >>I think one possible way is to clear the software tlb on entry to the >>transaction and disable (not install any translations) the software >>TLB till the end of the transaction. >>In the softmmu helper functions, the memory addresses as well as >>value can then be tracked in a hashtable and committed to system >>memory once the transaction is ready to be committed. > > I believe the transaction conflicts are handled post-translation by the cache > coherency protocol. Trying to store the pre-translation address isn't > sufficient for conflict resolution. > > Consider two virtual addresses that point to the same physical address. One > thread uses the first virtual address in a transaction; another thread writes > to the second virtual address while the transaction is going on. This should > cause the transaction to fail because the same physical address was involved. That's not really relevant. The important part is that no TLB hits are made within TCG, so that we always use the softmmu helpers. Incidentally, that's also accomplished by bits such as TLB_NOTDIRTY. We could add another bit so that pages referenced by TM don't need to be fetched out of the page tables every time. r~