Re: [Qemu-devel] [PATCH 2/2] target-mips: add missing MSA and correct FP in VMState

[Richard Henderson <rth@twiddle.net>]

On 02/18/2015 06:51 AM, Leon Alrae wrote:
>  static VMStateField vmstate_fpu_fields[] = {
>      VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32),
> -    VMSTATE_INT8(fp_status.float_detect_tininess, CPUMIPSFPUContext),
> +    VMSTATE_UINT8(fp_status.flush_to_zero, CPUMIPSFPUContext),
>      VMSTATE_INT8(fp_status.float_rounding_mode, CPUMIPSFPUContext),
>      VMSTATE_INT8(fp_status.float_exception_flags, CPUMIPSFPUContext),
>      VMSTATE_UINT32(fcr0, CPUMIPSFPUContext),
> @@ -70,6 +78,11 @@ static VMStateField vmstate_tc_fields[] = {
>      VMSTATE_UINTTL(CP0_TCScheFBack, TCState),
>      VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
>      VMSTATE_UINTTL(CP0_UserLocal, TCState),
> +    VMSTATE_INT32(msacsr, TCState),
> +    VMSTATE_INT8(msa_fp_status.float_rounding_mode, TCState),
> +    VMSTATE_INT8(msa_fp_status.float_exception_flags, TCState),
> +    VMSTATE_UINT8(msa_fp_status.flush_to_zero, TCState),
> +    VMSTATE_UINT8(msa_fp_status.flush_inputs_to_zero, TCState),
>      VMSTATE_END_OF_LIST()
>  };

Surely these fp_status fields are simply implementation of the architectural
CSR registers?

IMO you shouldn't store things related to TCG state, but always how the
architecture represents it.  That way you're free to change the TCG
implementation without breaking save/restore.


r~