From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52914) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YOodr-0000oQ-5D for qemu-devel@nongnu.org; Fri, 20 Feb 2015 09:33:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YOodn-00034j-Ln for qemu-devel@nongnu.org; Fri, 20 Feb 2015 09:33:19 -0500 Message-ID: <54E745A7.7070908@suse.de> Date: Fri, 20 Feb 2015 15:33:11 +0100 From: Alexander Graf MIME-Version: 1.0 References: <1424080457-13752-1-git-send-email-marcel@redhat.com> <1424080457-13752-15-git-send-email-marcel@redhat.com> <54E1E9E4.6060202@suse.de> <54E1F0C6.9020006@redhat.com> In-Reply-To: <54E1F0C6.9020006@redhat.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH RFC V2 14/17] hw/pci: piix - suport multiple host bridges List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Marcel Apfelbaum , qemu-devel@nongnu.org Cc: seabios@seabios.org, kraxel@redhat.com, mst@redhat.com, quintela@redhat.com, alex.williamson@redhat.com, kevin@koconnor.net, qemu-ppc@nongnu.org, hare@suse.de, imammedo@redhat.com, amit.shah@redhat.com, pbonzini@redhat.com, leon.alrae@imgtec.com, aurelien@aurel32.net, rth@twiddle.net On 16.02.15 14:29, Marcel Apfelbaum wrote: > On 02/16/2015 03:00 PM, Alexander Graf wrote: >> >> >> On 16.02.15 10:54, Marcel Apfelbaum wrote: >>> From: Marcel Apfelbaum >>> >>> Instead of assuming it has only one bus, it >>> enumerates all the host bridges until it finds >>> the one with bus number corresponding with the >>> config register. >>> >>> Signed-off-by: Marcel Apfelbaum >> > Hi Alexander, > Thank you for the review. > > >> How 440 specific is this? Wouldn't we need similar code for q35 and gpxe? > For gpxe: I have no idea. > For Q35: PCI Express have native support for extra root bridges by > having multiple Root Complexes(RC), but in this case each RC > handles its separate configuration space. > > It may be possible to use the same hack as in PC to expose a > PCIe Root Port as a different host bridge and a primary bus behind > it, but it is out of this series scope. > > The series aims to address the limitation that PC machines support > NUMA nodes for CPU/memory but not PCI. > > Anyway, we can move the code when neeeded, but since it will > take some and the implementation is not certain, for the moment > is 440 specific. Sorry, I didn't realize that this was legacy PCI specific :). Alex