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From: Chen Gang S <gang.chen@sunrus.com.cn>
To: Richard Henderson <rth@redhat.com>,
	Peter Maydell <peter.maydell@linaro.org>,
	Chris Metcalf <cmetcalf@ezchip.com>
Cc: "walt@tilera.com" <walt@tilera.com>,
	Riku Voipio <riku.voipio@iki.fi>,
	qemu-devel <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH] target-tilegx: Execute _start and reach to __libc_start_main successfully
Date: Wed, 25 Feb 2015 01:08:18 +0800	[thread overview]
Message-ID: <54ECB002.8070907@sunrus.com.cn> (raw)
In-Reply-To: <54ECA9F3.3060903@redhat.com>

On 2/25/15 00:42, Richard Henderson wrote:
> On 02/24/2015 05:39 AM, Chen Gang S wrote:
>> After read through target-arm/translate-a64.c, I guess, the main reason
>> is: the zero register (r31) shares with the sp register (also r31).
>>
>>  - So it uses cpu_reg() and cpu_reg_sp() for them.
>>
>>  - For each zero register access, it will new a tcg temporary variable
>>    for it, and release it after finish decoding one insn (so it will not
>>    overwrite sp register.).
>>
>> For tilegx, zero register (r63) does not share with other registers (sp
>> is r54), so we needn't use wrap functions for it.
> 
> Perhaps aarch64 is confusing for you.  But Alpha also has zero registers, and
> also uses wrapper functions.  See load_gpr and dest_gpr.
> 
> The very most important reason to use a wrapper, and thus a tcg temporary that
> keeps getting re-initialized to zero, is that the tcg optimizer gets to see
> that zero and optimize the code accordingly.
> 

OK, thanks, what you said above sounds reasonable to me, I shall use tcg
temporary variable for zero register, when I send patch v2.

Thanks.
-- 
Chen Gang

Open, share, and attitude like air, water, and life which God blessed

  reply	other threads:[~2015-02-24 17:00 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-02-24  7:53 [Qemu-devel] [PATCH] target-tilegx: Execute _start and reach to __libc_start_main successfully Chen Gang S
2015-02-24  8:07 ` Chen Gang S
2015-02-24 14:21 ` Chris Metcalf
2015-02-24 14:38   ` Peter Maydell
2015-02-24 15:39     ` Chen Gang S
2015-02-24 16:42       ` Richard Henderson
2015-02-24 17:08         ` Chen Gang S [this message]
2015-02-24 16:31   ` Chen Gang S
2015-02-24 16:46     ` Chris Metcalf
2015-02-24 17:25       ` Chen Gang S
2015-02-24 18:18         ` Chris Metcalf
2015-02-25  1:01           ` Chen Gang S
2015-02-24 17:55 ` Richard Henderson
2015-02-25  3:40   ` Chen Gang S
2015-02-25 17:19     ` Richard Henderson
2015-02-26  1:44       ` Chen Gang S
2015-02-26 16:31         ` Richard Henderson
2015-02-26 23:30           ` Chen Gang S
2015-02-27  3:01         ` Chris Metcalf
2015-02-27  3:41           ` Chen Gang S

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