From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37274) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YVOji-0002D6-3L for qemu-devel@nongnu.org; Tue, 10 Mar 2015 14:18:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YVOjd-0000y6-48 for qemu-devel@nongnu.org; Tue, 10 Mar 2015 14:18:34 -0400 Received: from mail-qc0-x235.google.com ([2607:f8b0:400d:c01::235]:34483) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YVOjc-0000xq-UI for qemu-devel@nongnu.org; Tue, 10 Mar 2015 14:18:29 -0400 Received: by qcvp6 with SMTP id p6so4133260qcv.1 for ; Tue, 10 Mar 2015 11:18:28 -0700 (PDT) Sender: Richard Henderson Message-ID: <54FF356F.4060805@twiddle.net> Date: Tue, 10 Mar 2015 11:18:23 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1424380469-20138-1-git-send-email-rth@twiddle.net> <1424380469-20138-3-git-send-email-rth@twiddle.net> In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 02/11] target-arm: Extend NZCF to 64 bits List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: QEMU Developers On 03/10/2015 09:08 AM, Peter Maydell wrote: > On 19 February 2015 at 21:14, Richard Henderson wrote: >> The resulting aarch64 translation is a bit cleaner. >> Sign-extending from 32-bits is simpler than having >> to use setcond to narrow from 64-bits. >> >> Signed-off-by: Richard Henderson > > >> @@ -4545,6 +4548,9 @@ void aarch64_sync_64_to_32(CPUARMState *env) >> env->regs[i] = env->xregs[i]; >> } >> >> + /* Need to compress Z into the low bits. */ >> + env->ZF = (env->ZF != 0); >> + > > I really don't like this. Having state with a different format > in 32-bit and 64-bit modes is asking for trouble -- the bits > we already have to convert are already awkward enough. > > I'd much rather we stuck with a format where env->ZF is > the same regardless of register width, as we have now. Err.. it is the same format, from the viewpoint of outside TCG generated code. >>From the viewpoint inside TCG generated code, for AArch32, ZF is only 32-bits wide. For AArch64, ZF is 64-bits wide. So when we transition from AArch64 to AArch32, we must make sure that if ZF != 0, then ZF <= 0xffffffff. It's a similar concept for NF and VF, except there I can arrange for the sign bit of the 32-bit AArch32 NF/VF to line up with the 64-bit AArch64 NF/VF in memory. If that's not what you mean... then I don't know what you mean. r~