From: Richard Henderson <richard.henderson@linaro.org>
To: "Alex Bennée" <alex.bennee@linaro.org>
Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org
Subject: Re: [Qemu-devel] [RFC PATCH 19/30] Fix mask for AdvancedSIMD 2 reg misc
Date: Mon, 16 Oct 2017 16:47:31 -0700 [thread overview]
Message-ID: <54b36f17-4e9d-bb9e-6d2d-b1df1ef44480@linaro.org> (raw)
In-Reply-To: <20171013162438.32458-20-alex.bennee@linaro.org>
On 10/13/2017 09:24 AM, Alex Bennée wrote:
> While the group encoding declares bit 28 a zero it is set for
> FCMGT (zero)
I see that's what the documentation says. Have you validated this? It really
seems like an isolated typo. Even if that is right, it isn't (documented) to
be set for the other simd_two_reg_misc_fp16 instructions. So that means the
rest of your decode is compromised.
This patch needs folding into previous, anyway.
r~
next prev parent reply other threads:[~2017-10-16 23:47 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 01/30] linux-user/main: support dfilter Alex Bennée
2017-10-13 20:36 ` Richard Henderson
2017-10-14 9:58 ` Laurent Vivier
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 02/30] arm: introduce ARM_V8_FP16 feature bit Alex Bennée
2017-10-13 20:44 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 03/30] include/exec/helper-head.h: support f16 in helper calls Alex Bennée
2017-10-13 20:44 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 04/30] target/arm/cpu.h: update comment for half-precision values Alex Bennée
2017-10-13 20:44 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 05/30] softfloat: implement propagateFloat16NaN Alex Bennée
2017-10-13 20:49 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 06/30] fpu/softfloat: implement float16_squash_input_denormal Alex Bennée
2017-10-13 20:51 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 07/30] fpu/softfloat: implement float16_abs helper Alex Bennée
2017-10-13 20:51 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 08/30] softfloat: add half-precision expansions for MINMAX fns Alex Bennée
2017-10-13 20:52 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 09/30] softfloat: propagate signalling NaNs in MINMAX Alex Bennée
2017-10-15 16:13 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 10/30] softfloat: improve comments on ARM NaN propagation Alex Bennée
2017-10-15 16:14 ` Richard Henderson
2017-10-15 16:54 ` Peter Maydell
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 11/30] target/arm: implement half-precision F(MIN|MAX)(V|NMV) Alex Bennée
2017-10-16 20:10 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 12/30] target/arm/translate-a64.c: handle_3same_64 comment fix Alex Bennée
2017-10-15 16:28 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 13/30] target/arm/translate-a64.c: AdvSIMD scalar 3 Same FP16 initial decode Alex Bennée
2017-10-16 20:16 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 14/30] softfloat: 16 bit helpers for shr, clz and rounding and packing Alex Bennée
2017-10-15 18:02 ` Richard Henderson
2017-10-16 8:20 ` Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 15/30] softfloat: half-precision add/sub/mul/div support Alex Bennée
2017-10-16 22:01 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 16/30] target/arm/translate-a64.c: add FP16 FADD/FMUL/FDIV to AdvSIMD 3 Same (!sub) Alex Bennée
2017-10-16 22:08 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 17/30] target/arm/translate-a64.c: add FP16 FMULX Alex Bennée
2017-10-16 22:24 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 18/30] target/arm/translate-a64.c: add AdvSIMD scalar two-reg misc skeleton Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 19/30] Fix mask for AdvancedSIMD 2 reg misc Alex Bennée
2017-10-16 23:47 ` Richard Henderson [this message]
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 20/30] softfloat: half-precision compare functions Alex Bennée
2017-10-17 0:06 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 21/30] target/arm/translate-a64: add FP16 2-reg misc compare (zero) Alex Bennée
2017-10-17 0:36 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 22/30] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same Alex Bennée
2017-10-17 0:39 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 23/30] softfloat: add float16_rem and float16_muladd (!CHECK) Alex Bennée
2017-10-17 2:17 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 24/30] disas_simd_indexed: support half-precision operations Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 25/30] softfloat: float16_round_to_int Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 26/30] tests/test-softfloat: add a simple test framework Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 27/30] target/arm/translate-a64.c: add FP16 FRINTP to 2 reg misc Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 28/30] softfloat: float16_to_int16 conversion Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 29/30] tests/test-softfloat: add f16_to_int16 conversion test Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 30/30] target/arm/translate-a64.c: add FP16 FCVTPS to 2 reg misc Alex Bennée
2017-10-13 16:58 ` [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) no-reply
2017-10-13 16:59 ` no-reply
2017-10-17 2:34 ` Richard Henderson
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