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From: Richard Henderson <richard.henderson@linaro.org>
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Date: Tue, 12 Sep 2017 06:52:44 -0700
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Subject: Re: [Qemu-devel] [PATCH 8/8] tcg/i386: Add vector operations
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To: =?UTF-8?Q?Alex_Benn=c3=a9e?= <alex.bennee@linaro.org>
Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org

On 09/11/2017 02:07 AM, Alex Bennée wrote:
> 
> Richard Henderson <richard.henderson@linaro.org> writes:
> 
>> On 09/08/2017 06:10 AM, Alex Bennée wrote:
>>> Also this commit breaks RISU:
>>>
>>>  qemu-aarch64 build/aarch64-linux-gnu/risu
>>>     testcases.aarch64/insn_ANDSi_RES8_ANDS_RES_ANDv_ASRV__INC.risu.bin \
>>>     -t testcases.aarch64/insn_ANDSi_RES8_ANDS_RES_ANDv_ASRV__INC.risu.bin.trace
>>>
>>> Gives:
>>>
>>> mismatch detail (master : apprentice):
>>>   V29   : 000000000000000005388083c1444242 vs 00000000000000002a000e0416a30018
>>>
>>> The insn is:
>>>
>>>   37c:       6f56a29d        umull2  v29.4s, v20.8h, v6.h[1]
>>>
>>> Which is odd because I didn't think we'd touched that.
>>
>> Indeed we didn't.  Still, I'll check it out next week.
> 
> OK it would help if I had objdumped the right file:
> 
>      36c:       0e781fdd        bic     v29.8b, v30.8b, v24.8b
>      370:       00005af0        .inst   0x00005af0 ; undefined

Thanks.  The sse pandn operand order is ... surprising.
Even though I know that I still managed to get it wrong.
Fixed for v2.


r~