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[109.43.179.131]) by smtp.gmail.com with ESMTPSA id l30-20020a05600c1d1e00b003a601a1c2f7sm2827366wms.19.2022.09.21.03.59.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Sep 2022 03:59:17 -0700 (PDT) Message-ID: <54b9d848-8ba4-216b-3267-69958f363c0c@redhat.com> Date: Wed, 21 Sep 2022 12:59:16 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 Subject: Re: [PATCH v7 2/2] target/s390x: support PRNO_TRNG instruction Content-Language: en-US To: "Jason A. Donenfeld" Cc: David Hildenbrand , qemu-s390x@nongnu.org, qemu-devel@nongnu.org, Christian Borntraeger , Richard Henderson , Cornelia Huck , Harald Freudenberger , Holger Dengler References: <20220809150331.84296-1-Jason@zx2c4.com> <20220809150331.84296-2-Jason@zx2c4.com> <4b1352d4-4dff-7ab7-4c96-3fed4f52dd77@redhat.com> From: Thomas Huth In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -49 X-Spam_score: -5.0 X-Spam_bar: ----- X-Spam_report: (-5.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.182, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 29/08/2022 18.29, Jason A. Donenfeld wrote: > On Fri, Aug 26, 2022 at 01:28:11PM +0200, Thomas Huth wrote: >>> + qemu_guest_getrandom_nofail(tmp, block); >>> + for (size_t i = 0; i < block; ++i) { >>> + cpu_stb_data_ra(env, wrap_address(env, *buf_reg), tmp[i], ra); >>> + *buf_reg = deposit64(*buf_reg, 0, message_reg_len, *buf_reg + 1); >>> + --*len_reg; >> >> I know it's annoying, but technically, you must not touch the upper bits of >> the len_reg if running in 31- or 24-bit addressing mode. The Principles of >> Operations say: >> >> "In either the 24- or 31-bit addressing mode, bits 32-63 of the odd-numbered >> register are decremented by the number >> of bytes processed for the respective operand, and >> bits 0-31 of the register remain unchanged." >> > > This is what I was trying to do with the use of deposit64, following > David's guidance. Did I mess something up? Sorry for not following up earlier - I've been away from keyboard for a couple of weeks... Anyway, that was likely a wrong comment from my side anyway - I thought that "--*len_reg" might alter the upper bits, too, when there is no masking here. But since "len" has been constrained earlier in the function already, I think this cannot happen, so please never mind. I just saw that you also sent a v8 now, so I'll follow up on that version. Thomas