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To: Paolo Savini , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Helene Chelin , Nathan Egge , Max Chou References: <20241029194348.59574-1-paolo.savini@embecosm.com> <20241029194348.59574-3-paolo.savini@embecosm.com> <7a046c99-c4e7-4395-8dc9-9139e9bfba06@linaro.org> <96e7601d-14aa-4741-8f6a-ae4a1c397a44@embecosm.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <96e7601d-14aa-4741-8f6a-ae4a1c397a44@embecosm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/30/24 15:25, Paolo Savini wrote: > Thanks for the review Richard. > > On 10/30/24 11:40, Richard Henderson wrote: >> On 10/29/24 19:43, Paolo Savini wrote: >>> This patch optimizes the emulation of unit-stride load/store RVV instructions >>> when the data being loaded/stored per iteration amounts to 16 bytes or more. >>> The optimization consists of calling __builtin_memcpy on chunks of data of 16 >>> bytes between the memory address of the simulated vector register and the >>> destination memory address and vice versa. >>> This is done only if we have direct access to the RAM of the host machine, >>> if the host is little endiand and if it supports atomic 128 bit memory >>> operations. >>> >>> Signed-off-by: Paolo Savini >>> --- >>>   target/riscv/vector_helper.c    | 17 ++++++++++++++++- >>>   target/riscv/vector_internals.h | 12 ++++++++++++ >>>   2 files changed, 28 insertions(+), 1 deletion(-) >>> >>> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c >>> index 75c24653f0..e1c100e907 100644 >>> --- a/target/riscv/vector_helper.c >>> +++ b/target/riscv/vector_helper.c >>> @@ -488,7 +488,22 @@ vext_group_ldst_host(CPURISCVState *env, void *vd, uint32_t byte_end, >>>       } >>>         fn = fns[is_load][group_size]; >>> -    fn(vd, byte_offset, host + byte_offset); >>> + >>> +    /* __builtin_memcpy uses host 16 bytes vector loads and stores if supported. >>> +     * We need to make sure that these instructions have guarantees of atomicity. >>> +     * E.g. x86 processors provide strong guarantees of atomicity for 16-byte >>> +     * memory operations if the memory operands are 16-byte aligned */ >>> +    if (!HOST_BIG_ENDIAN && (byte_offset + 16 < byte_end) && >>> +            ((byte_offset % 16) == 0) && HOST_128_ATOMIC_MEM_OP) { >>> +      group_size = MO_128; >>> +      if (is_load) { >>> +        __builtin_memcpy((uint8_t *)(vd + byte_offset), (uint8_t *)(host + >>> byte_offset), 16); >>> +      } else { >>> +        __builtin_memcpy((uint8_t *)(host + byte_offset), (uint8_t *)(vd + >>> byte_offset), 16); >>> +      } >> >> I said this last time and I'll say it again: >> >>     __builtin_memcpy DOES NOT equal VMOVDQA > I am aware of this. I took __builtin_memcpy as a generic enough way to emulate loads and > stores that should allow several hosts to generate the widest load/store instructions they > can and on x86 I see this generates instructions vmovdpu/movdqu that are not always > guaranteed to be atomic. x86 though guarantees them to be atomic if the memory address is > aligned to 16 bytes. No, AMD guarantees MOVDQU is atomic if aligned, Intel does not. See the comment in util/cpuinfo-i386.c, and the two CPUINFO_ATOMIC_VMOVDQ[AU] bits. See also host/include/*/host/atomic128-ldst.h, HAVE_ATOMIC128_RO, and atomic16_read_ro. Not that I think you should use that here; it's complicated, and I think you're better off relying on the code in accel/tcg/ when more than byte atomicity is required. r~