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[187.189.51.143]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-71d725476fesm2844656a34.28.2024.12.03.06.09.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Dec 2024 06:09:17 -0800 (PST) Message-ID: <54d6068b-49f6-42c5-aff6-dd4fa61579ff@linaro.org> Date: Tue, 3 Dec 2024 08:09:14 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 42/67] target/arm: Convert handle_rev to decodetree To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20241201150607.12812-1-richard.henderson@linaro.org> <20241201150607.12812-43-richard.henderson@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2001:4860:4864:20::2c; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 12/3/24 05:49, Peter Maydell wrote: > On Sun, 1 Dec 2024 at 15:16, Richard Henderson > wrote: >> >> This includes REV16, REV32, REV64. >> >> Signed-off-by: Richard Henderson >> --- > >> @@ -10070,10 +10003,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) >> TCGv_ptr tcg_fpstatus; >> >> switch (opcode) { >> - case 0x0: /* REV64, REV32 */ >> - case 0x1: /* REV16 */ >> - handle_rev(s, opcode, u, is_q, size, rn, rd); >> - return; >> case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */ >> case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */ >> if (size == 3) { >> @@ -10276,6 +10205,8 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) >> break; >> } >> default: >> + case 0x0: /* REV64 */ >> + case 0x1: /* REV16, REV32 */ > > REV32 is case 0x0, not 0x1, per the comments deleted above. > >> case 0x3: /* SUQADD, USQADD */ >> case 0x4: /* CLS, CLZ */ >> case 0x5: /* CNT, NOT, RBIT */ >> diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode >> index 4f8231d07a..2531809096 100644 >> --- a/target/arm/tcg/a64.decode >> +++ b/target/arm/tcg/a64.decode >> @@ -73,6 +73,7 @@ >> >> @qrr_b . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=0 >> @qrr_h . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=1 >> +@qrr_bh . q:1 ...... . esz:1 ...... ...... rn:5 rd:5 &qrr_e >> @qrr_e . q:1 ...... esz:2 ...... ...... rn:5 rd:5 &qrr_e >> >> @qrrr_b . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=0 >> @@ -1657,3 +1658,7 @@ CMGE0_v 0.10 1110 ..1 00000 10001 0 ..... ..... @qrr_e >> CMEQ0_v 0.00 1110 ..1 00000 10011 0 ..... ..... @qrr_e >> CMLE0_v 0.10 1110 ..1 00000 10011 0 ..... ..... @qrr_e >> CMLT0_v 0.00 1110 ..1 00000 10101 0 ..... ..... @qrr_e >> + >> +REV16_v 0.00 1110 001 00000 00011 0 ..... ..... @qrr_b >> +REV32_v 0.10 1110 0.1 00000 00011 0 ..... ..... @qrr_bh >> +REV64_v 0.00 1110 ..1 00000 00001 0 ..... ..... @qrr_e > > This doesn't look quite right -- in the decode table in C4.1.96.21, > 2-reg misc REV32 is opcode 00000, like REV64, not 00001 like REV16. > > --- a/target/arm/tcg/a64.decode > +++ b/target/arm/tcg/a64.decode > @@ -1660,5 +1660,5 @@ CMLE0_v 0.10 1110 ..1 00000 10011 0 > ..... ..... @qrr_e > CMLT0_v 0.00 1110 ..1 00000 10101 0 ..... ..... @qrr_e > > REV16_v 0.00 1110 001 00000 00011 0 ..... ..... @qrr_b > -REV32_v 0.10 1110 0.1 00000 00011 0 ..... ..... @qrr_bh > +REV32_v 0.10 1110 0.1 00000 00001 0 ..... ..... @qrr_bh > REV64_v 0.00 1110 ..1 00000 00001 0 ..... ..... @qrr_e > > should I think be the right fixup. Yep, my bad. I remember "fixing" the comment, because I thought it was off. I must have been tired, or something. Odd that this passes risu... maybe we're missing a pattern. r~