From: Miles Glenn <milesg@linux.ibm.com>
To: Nicholas Piggin <npiggin@gmail.com>, qemu-ppc@nongnu.org
Cc: qemu-devel@nongnu.org, "Frédéric Barrat" <fbarrat@linux.ibm.com>,
"Michael Kowal" <kowal@linux.ibm.com>,
"Caleb Schlossin" <calebs@linux.vnet.ibm.com>
Subject: Re: [PATCH 35/50] ppc/xive: Add xive_tctx_pipr_set() helper function
Date: Thu, 15 May 2025 11:05:23 -0500 [thread overview]
Message-ID: <54f087b21d501fd68648f6b07229d6d14f64b8e4.camel@linux.ibm.com> (raw)
In-Reply-To: <20250512031100.439842-36-npiggin@gmail.com>
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
On Mon, 2025-05-12 at 13:10 +1000, Nicholas Piggin wrote:
> Have xive_tctx_notify() also set the new PIPR value and rename it to
> xive_tctx_pipr_set(). This can replace the last xive_tctx_pipr_update()
> caller because it does not need to update IPB (it already sets it).
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> hw/intc/xive.c | 39 +++++++++++----------------------------
> hw/intc/xive2.c | 16 +++++++---------
> include/hw/ppc/xive.h | 5 ++---
> 3 files changed, 20 insertions(+), 40 deletions(-)
>
> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> index d5dbeab6bd..4659821d4a 100644
> --- a/hw/intc/xive.c
> +++ b/hw/intc/xive.c
> @@ -125,12 +125,16 @@ uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t sig_ring)
> return ((uint64_t)nsr << 8) | sig_regs[TM_CPPR];
> }
>
> -void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring, uint8_t group_level)
> +/* Change PIPR and calculate NSR and irq based on PIPR, CPPR, group */
> +void xive_tctx_pipr_set(XiveTCTX *tctx, uint8_t ring, uint8_t pipr,
> + uint8_t group_level)
> {
> uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring);
> uint8_t *regs = &tctx->regs[ring];
>
> - if (sig_regs[TM_PIPR] < sig_regs[TM_CPPR]) {
> + sig_regs[TM_PIPR] = pipr;
> +
> + if (pipr < sig_regs[TM_CPPR]) {
> switch (ring) {
> case TM_QW1_OS:
> sig_regs[TM_NSR] = TM_QW1_NSR_EO | (group_level & 0x3F);
> @@ -145,7 +149,7 @@ void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring, uint8_t group_level)
> g_assert_not_reached();
> }
> trace_xive_tctx_notify(tctx->cs->cpu_index, ring,
> - regs[TM_IPB], sig_regs[TM_PIPR],
> + regs[TM_IPB], pipr,
> sig_regs[TM_CPPR], sig_regs[TM_NSR]);
> qemu_irq_raise(xive_tctx_output(tctx, ring));
> } else {
> @@ -213,29 +217,10 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr)
> }
> }
>
> - sig_regs[TM_PIPR] = pipr_min;
> -
> - /* CPPR has changed, check if we need to raise a pending exception */
> - xive_tctx_notify(tctx, ring_min, 0);
> + /* CPPR has changed, this may present or preclude a pending exception */
> + xive_tctx_pipr_set(tctx, ring_min, pipr_min, 0);
> }
>
> -void xive_tctx_pipr_update(XiveTCTX *tctx, uint8_t ring, uint8_t priority,
> - uint8_t group_level)
> -{
> - uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring);
> - uint8_t *regs = &tctx->regs[ring];
> -
> - if (group_level == 0) {
> - /* VP-specific */
> - regs[TM_IPB] |= xive_priority_to_ipb(priority);
> - sig_regs[TM_PIPR] = xive_ipb_to_pipr(regs[TM_IPB]);
> - } else {
> - /* VP-group */
> - sig_regs[TM_PIPR] = xive_priority_to_pipr(priority);
> - }
> - xive_tctx_notify(tctx, ring, group_level);
> - }
> -
> static void xive_tctx_pipr_recompute_from_ipb(XiveTCTX *tctx, uint8_t ring)
> {
> uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring);
> @@ -244,8 +229,7 @@ static void xive_tctx_pipr_recompute_from_ipb(XiveTCTX *tctx, uint8_t ring)
> /* Does not support a presented group interrupt */
> g_assert(!xive_nsr_indicates_group_exception(ring, sig_regs[TM_NSR]));
>
> - sig_regs[TM_PIPR] = xive_ipb_to_pipr(regs[TM_IPB]);
> - xive_tctx_notify(tctx, ring, 0);
> + xive_tctx_pipr_set(tctx, ring, xive_ipb_to_pipr(regs[TM_IPB]), 0);
> }
>
> void xive_tctx_pipr_present(XiveTCTX *tctx, uint8_t ring, uint8_t priority,
> @@ -264,8 +248,7 @@ void xive_tctx_pipr_present(XiveTCTX *tctx, uint8_t ring, uint8_t priority,
> }
> g_assert(pipr <= xive_ipb_to_pipr(regs[TM_IPB]));
> g_assert(pipr < sig_regs[TM_PIPR]);
> - sig_regs[TM_PIPR] = pipr;
> - xive_tctx_notify(tctx, ring, group_level);
> + xive_tctx_pipr_set(tctx, ring, pipr, group_level);
> }
>
> /*
> diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
> index b9ee8c9e9f..8c8dab3aa2 100644
> --- a/hw/intc/xive2.c
> +++ b/hw/intc/xive2.c
> @@ -966,10 +966,10 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx,
> }
>
> /*
> - * Compute the PIPR based on the restored state.
> + * Set the PIPR/NSR based on the restored state.
> * It will raise the External interrupt signal if needed.
> */
> - xive_tctx_pipr_update(tctx, TM_QW1_OS, backlog_prio, backlog_level);
> + xive_tctx_pipr_set(tctx, TM_QW1_OS, backlog_prio, backlog_level);
> }
>
> /*
> @@ -1144,8 +1144,7 @@ static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr)
> }
>
> /* interrupt is VP directed, pending in IPB */
> - sig_regs[TM_PIPR] = cppr;
> - xive_tctx_notify(tctx, ring, 0); /* Ensure interrupt is cleared */
> + xive_tctx_pipr_set(tctx, ring, cppr, 0);
> return;
> } else {
> /* CPPR was lowered, but still above PIPR. No action needed. */
> @@ -1255,11 +1254,10 @@ again:
> pipr_min = backlog_prio;
> }
>
> - /* PIPR should not be set to a value greater than CPPR */
> - sig_regs[TM_PIPR] = (pipr_min > cppr) ? cppr : pipr_min;
> -
> - /* CPPR has changed, check if we need to raise a pending exception */
> - xive_tctx_notify(tctx, ring_min, group_level);
> + if (pipr_min > cppr) {
> + pipr_min = cppr;
> + }
> + xive_tctx_pipr_set(tctx, ring_min, pipr_min, group_level);
> }
>
> void xive2_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx,
> diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
> index a3c2f50ece..2372d1014b 100644
> --- a/include/hw/ppc/xive.h
> +++ b/include/hw/ppc/xive.h
> @@ -584,12 +584,11 @@ void xive_tctx_pic_print_info(XiveTCTX *tctx, GString *buf);
> Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp);
> void xive_tctx_reset(XiveTCTX *tctx);
> void xive_tctx_destroy(XiveTCTX *tctx);
> -void xive_tctx_pipr_update(XiveTCTX *tctx, uint8_t ring, uint8_t priority,
> - uint8_t group_level);
> +void xive_tctx_pipr_set(XiveTCTX *tctx, uint8_t ring, uint8_t priority,
> + uint8_t group_level);
> void xive_tctx_pipr_present(XiveTCTX *tctx, uint8_t ring, uint8_t priority,
> uint8_t group_level);
> void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t ring);
> -void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring, uint8_t group_level);
> uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring);
>
> /*
next prev parent reply other threads:[~2025-05-15 16:06 UTC|newest]
Thread overview: 192+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-12 3:10 [PATCH 00/50] ppc/xive: updates for PowerVM Nicholas Piggin
2025-05-12 3:10 ` [PATCH 01/50] ppc/xive: Fix xive trace event output Nicholas Piggin
2025-05-14 14:26 ` Caleb Schlossin
2025-05-14 18:41 ` Mike Kowal
2025-05-15 15:30 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 02/50] ppc/xive: Report access size in XIVE TM operation error logs Nicholas Piggin
2025-05-14 14:27 ` Caleb Schlossin
2025-05-14 18:42 ` Mike Kowal
2025-05-15 15:31 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 03/50] ppc/xive2: Fix calculation of END queue sizes Nicholas Piggin
2025-05-14 14:27 ` Caleb Schlossin
2025-05-14 18:45 ` Mike Kowal
2025-05-16 0:06 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 04/50] ppc/xive2: Remote VSDs need to match on forwarding address Nicholas Piggin
2025-05-14 14:27 ` Caleb Schlossin
2025-05-14 18:46 ` Mike Kowal
2025-05-15 15:34 ` Miles Glenn
2025-05-16 0:08 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 05/50] ppc/xive2: fix context push calculation of IPB priority Nicholas Piggin
2025-05-14 14:30 ` Caleb Schlossin
2025-05-14 18:48 ` Mike Kowal
2025-05-15 15:36 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 06/50] ppc/xive: Fix PHYS NSR ring matching Nicholas Piggin
2025-05-14 14:30 ` Caleb Schlossin
2025-05-14 18:49 ` Mike Kowal
2025-05-15 15:39 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 07/50] ppc/xive2: Reset Generation Flipped bit on END Cache Watch Nicholas Piggin
2025-05-14 14:30 ` Caleb Schlossin
2025-05-14 18:50 ` Mike Kowal
2025-05-15 15:41 ` Miles Glenn
2025-05-16 0:09 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 08/50] ppc/xive2: Use fair irq target search algorithm Nicholas Piggin
2025-05-14 14:31 ` Caleb Schlossin
2025-05-14 18:51 ` Mike Kowal
2025-05-15 15:42 ` Miles Glenn
2025-05-16 0:12 ` Nicholas Piggin
2025-05-16 16:22 ` Mike Kowal
2025-05-12 3:10 ` [PATCH 09/50] ppc/xive2: Fix irq preempted by lower priority group irq Nicholas Piggin
2025-05-14 14:31 ` Caleb Schlossin
2025-05-14 18:52 ` Mike Kowal
2025-05-16 0:12 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 10/50] ppc/xive2: Fix treatment of PIPR in CPPR update Nicholas Piggin
2025-05-14 14:32 ` Caleb Schlossin
2025-05-14 18:53 ` Mike Kowal
2025-05-16 0:15 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 11/50] ppc/xive2: Do not present group interrupt on OS-push if precluded by CPPR Nicholas Piggin
2025-05-14 14:32 ` Caleb Schlossin
2025-05-14 18:54 ` Mike Kowal
2025-05-15 15:43 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 12/50] ppc/xive2: Set CPPR delivery should account for group priority Nicholas Piggin
2025-05-14 14:33 ` Caleb Schlossin
2025-05-14 18:57 ` Mike Kowal
2025-05-15 15:45 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 13/50] ppc/xive: tctx_notify should clear the precluded interrupt Nicholas Piggin
2025-05-14 14:33 ` Caleb Schlossin
2025-05-14 18:58 ` Mike Kowal
2025-05-15 15:46 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 14/50] ppc/xive: Explicitly zero NSR after accepting Nicholas Piggin
2025-05-14 14:34 ` Caleb Schlossin
2025-05-14 19:07 ` Mike Kowal
2025-05-15 23:31 ` Nicholas Piggin
2025-05-15 15:47 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 15/50] ppc/xive: Move NSR decoding into helper functions Nicholas Piggin
2025-05-14 14:35 ` Caleb Schlossin
2025-05-14 19:04 ` Mike Kowal
2025-05-15 15:48 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 16/50] ppc/xive: Fix pulling pool and phys contexts Nicholas Piggin
2025-05-14 14:36 ` Caleb Schlossin
2025-05-14 19:01 ` Mike Kowal
2025-05-15 15:49 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 17/50] pnv/xive2: Support ESB Escalation Nicholas Piggin
2025-05-14 14:36 ` Caleb Schlossin
2025-05-14 19:00 ` Mike Kowal
2025-05-16 0:05 ` Nicholas Piggin
2025-05-16 15:44 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 18/50] pnv/xive2: Print value in invalid register write logging Nicholas Piggin
2025-05-14 14:36 ` Caleb Schlossin
2025-05-14 19:09 ` Mike Kowal
2025-05-15 15:50 ` Miles Glenn
2025-05-16 0:15 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 19/50] pnv/xive2: VC_ENDC_WATCH_SPEC regs should read back WATCH_FULL Nicholas Piggin
2025-05-14 14:37 ` Caleb Schlossin
2025-05-14 19:10 ` Mike Kowal
2025-05-15 15:51 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 20/50] pnv/xive2: Permit valid writes to VC/PC Flush Control registers Nicholas Piggin
2025-05-14 14:37 ` Caleb Schlossin
2025-05-14 19:11 ` Mike Kowal
2025-05-15 15:52 ` Miles Glenn
2025-05-16 0:18 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 21/50] ppc/xive2: add interrupt priority configuration flags Nicholas Piggin
2025-05-14 19:41 ` Mike Kowal
2025-05-16 0:18 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 22/50] ppc/xive2: Support redistribution of group interrupts Nicholas Piggin
2025-05-14 19:42 ` Mike Kowal
2025-05-16 0:19 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 23/50] ppc/xive: Add more interrupt notification tracing Nicholas Piggin
2025-05-14 19:46 ` Mike Kowal
2025-05-16 0:19 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 24/50] ppc/xive2: Improve pool regs variable name Nicholas Piggin
2025-05-14 19:47 ` Mike Kowal
2025-05-16 0:19 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 25/50] ppc/xive2: Implement "Ack OS IRQ to even report line" TIMA op Nicholas Piggin
2025-05-14 19:48 ` Mike Kowal
2025-05-16 0:20 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 26/50] ppc/xive2: Redistribute group interrupt precluded by CPPR update Nicholas Piggin
2025-05-14 19:48 ` Mike Kowal
2025-05-16 0:20 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 27/50] ppc/xive2: redistribute irqs for pool and phys ctx pull Nicholas Piggin
2025-05-14 19:51 ` Mike Kowal
2025-05-12 3:10 ` [PATCH 28/50] ppc/xive: Change presenter .match_nvt to match not present Nicholas Piggin
2025-05-14 19:54 ` Mike Kowal
2025-05-15 23:40 ` Nicholas Piggin
2025-05-15 15:53 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 29/50] ppc/xive2: Redistribute group interrupt preempted by higher priority interrupt Nicholas Piggin
2025-05-14 19:55 ` Mike Kowal
2025-05-15 15:54 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 30/50] ppc/xive: Add xive_tctx_pipr_present() to present new interrupt Nicholas Piggin
2025-05-14 20:10 ` Mike Kowal
2025-05-15 15:21 ` Mike Kowal
2025-05-15 23:51 ` Nicholas Piggin
2025-05-15 23:43 ` Nicholas Piggin
2025-05-15 15:55 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 31/50] ppc/xive: Fix high prio group interrupt being preempted by low prio VP Nicholas Piggin
2025-05-15 15:21 ` Mike Kowal
2025-05-15 15:55 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 32/50] ppc/xive: Split xive recompute from IPB function Nicholas Piggin
2025-05-14 20:42 ` Mike Kowal
2025-05-15 23:46 ` Nicholas Piggin
2025-05-15 15:56 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 33/50] ppc/xive: tctx signaling registers rework Nicholas Piggin
2025-05-14 20:49 ` Mike Kowal
2025-05-15 15:58 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 34/50] ppc/xive: tctx_accept only lower irq line if an interrupt was presented Nicholas Piggin
2025-05-15 15:16 ` Mike Kowal
2025-05-15 23:50 ` Nicholas Piggin
2025-05-15 16:04 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 35/50] ppc/xive: Add xive_tctx_pipr_set() helper function Nicholas Piggin
2025-05-15 15:18 ` Mike Kowal
2025-05-15 16:05 ` Miles Glenn [this message]
2025-05-12 3:10 ` [PATCH 36/50] ppc/xive2: split tctx presentation processing from set CPPR Nicholas Piggin
2025-05-15 15:24 ` Mike Kowal
2025-05-15 16:06 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 37/50] ppc/xive2: Consolidate presentation processing in context push Nicholas Piggin
2025-05-15 15:25 ` Mike Kowal
2025-05-15 16:06 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 38/50] ppc/xive2: Avoid needless interrupt re-check on CPPR set Nicholas Piggin
2025-05-15 15:26 ` Mike Kowal
2025-05-15 16:07 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 39/50] ppc/xive: Assert group interrupts were redistributed Nicholas Piggin
2025-05-15 15:28 ` Mike Kowal
2025-05-15 16:08 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 40/50] ppc/xive2: implement NVP context save restore for POOL ring Nicholas Piggin
2025-05-15 15:36 ` Mike Kowal
2025-05-15 16:09 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 41/50] ppc/xive2: Prevent pulling of pool context losing phys interrupt Nicholas Piggin
2025-05-15 15:43 ` Mike Kowal
2025-05-15 16:10 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 42/50] ppc/xive: Redistribute phys after pulling of pool context Nicholas Piggin
2025-05-15 15:46 ` Mike Kowal
2025-05-15 16:11 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 43/50] ppc/xive: Check TIMA operations validity Nicholas Piggin
2025-05-15 15:47 ` Mike Kowal
2025-05-15 16:12 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 44/50] ppc/xive2: Implement pool context push TIMA op Nicholas Piggin
2025-05-15 15:48 ` Mike Kowal
2025-05-15 16:13 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 45/50] ppc/xive2: redistribute group interrupts on context push Nicholas Piggin
2025-05-15 15:44 ` Mike Kowal
2025-05-15 16:13 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 46/50] ppc/xive2: Implement set_os_pending TIMA op Nicholas Piggin
2025-05-15 15:49 ` Mike Kowal
2025-05-15 16:14 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 47/50] ppc/xive2: Implement POOL LGS push " Nicholas Piggin
2025-05-15 15:50 ` Mike Kowal
2025-05-15 16:15 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 48/50] ppc/xive2: Implement PHYS ring VP " Nicholas Piggin
2025-05-15 15:50 ` Mike Kowal
2025-05-15 16:16 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 49/50] ppc/xive: Split need_resend into restore_nvp Nicholas Piggin
2025-05-15 15:57 ` Mike Kowal
2025-05-15 16:16 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 50/50] ppc/xive2: Enable lower level contexts on VP push Nicholas Piggin
2025-05-15 15:54 ` Mike Kowal
2025-05-15 16:17 ` Miles Glenn
2025-05-15 15:36 ` [PATCH 00/50] ppc/xive: updates for PowerVM Cédric Le Goater
2025-05-16 1:29 ` Nicholas Piggin
2025-07-20 21:26 ` Cédric Le Goater
2025-08-04 17:37 ` Miles Glenn
2025-08-05 5:09 ` Cédric Le Goater
2025-08-05 15:52 ` Miles Glenn
2025-08-05 20:09 ` Cédric Le Goater
2025-07-03 9:37 ` Gautam Menghani
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