From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38052) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YYE9j-0004p0-66 for qemu-devel@nongnu.org; Wed, 18 Mar 2015 09:37:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YYE9e-00019N-3q for qemu-devel@nongnu.org; Wed, 18 Mar 2015 09:37:07 -0400 Message-ID: <55097F7A.7090809@suse.de> Date: Wed, 18 Mar 2015 14:36:58 +0100 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1426648281-13955-1-git-send-email-aik@ozlabs.ru> In-Reply-To: <1426648281-13955-1-git-send-email-aik@ozlabs.ru> Content-Type: text/plain; charset=iso-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH qemu] target-ppc: Remove never existed POWER5+ v0.0 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexey Kardashevskiy , qemu-devel@nongnu.org, Alexander Graf Cc: qemu-ppc@nongnu.org s/existed/existing/ or "that never existed" Am 18.03.2015 um 04:11 schrieb Alexey Kardashevskiy: > IBM uses low 16bits to specify a chip version of a POWER CPU. "specify the chip version of a" > So there has never been an actual silicon with PVR =3D 0x003B0000. > The first silicon would have PVR 0x003B0100 but it is very unlikely > to find it in any machine shipped to any customer as it is was too raw. "as it was" >=20 > This removes CPU_POWERPC_POWER5P_v00 definition and changes Maybe worth pointing out that the POWER5+_v0.0 QOM type was introduced in recent commit d7586dc426472b5ad0f5c01b5c7c551eeb5a6003 (target-ppc: Add versions to server CPU descriptions)? > POWER5+ and POWERgs aliases (which are synonyms) to point to > POWER5+_v2.1 which can still be found in real machines. FTR, 171777a4b38a0f6331ae60c2546a5baf84c4b359 (target-ppc: Turn POWER5gs CPU into alias for POWER5+) set the POWER5+ alias up as conflict resolution before I enabled the #ifdef TODO'ed POWER5P code in 35ebcb2b7a469739e6452d27379181bfbfc0388d (target-ppc: Prepare POWER5P CPU family). >=20 > Signed-off-by: Alexey Kardashevskiy > --- >=20 >=20 > I asked Paul. He suggested that there has never been an actual > POWER5 silicon with PVR which low 16 bits are zeroes, > the first one would be 0x003B0100 but it would be so buggy so > it would not be shipped to any real customer. > And then he suggested to look at the real POWER5+ machine, > we looked around and found one: >=20 > cpu : POWER5+ (gs) > clock : 1898.100000MHz > revision : 2.0 (pvr 003b 0200) >=20 > I believe 3b 0201 is also something real and it is defined already in Q= EMU > so here is a patch. Yes, I have a 2.1, so having POWER5+ point to it should be fine, it being the latest and now only one we have. Reviewed-by: Andreas F=E4rber Alex, can you tweak the commit message and apply this for 2.3 please, as fixup for the too hastily applied fix? > Yes, this does not touch the cpu family class registration issue, just > a tiny cleanup :) We can fix that for 2.4. :) Same for Alex' class cache that I just saw again. Thanks, Andreas --=20 SUSE Linux GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Felix Imend=F6rffer, Jane Smithard, Jennifer Guild, Dilip Upmanyu, Graham Norton; HRB 21284 (AG N=FCrnberg)