From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51461) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YYye4-0000B5-Kw for qemu-devel@nongnu.org; Fri, 20 Mar 2015 11:15:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YYye0-0000aW-Cy for qemu-devel@nongnu.org; Fri, 20 Mar 2015 11:15:32 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:43834) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YYye0-0000aR-6A for qemu-devel@nongnu.org; Fri, 20 Mar 2015 11:15:28 -0400 Message-ID: <550C4807.8090203@mail.uni-paderborn.de> Date: Fri, 20 Mar 2015 16:17:11 +0000 From: Bastian Koppelmann MIME-Version: 1.0 References: <1426862068-5710-1-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1426862068-5710-1-git-send-email-kbastian@mail.uni-paderborn.de> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] target-tricore: fix DVINIT_HU/BU calculating overflow before result List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On 03/20/2015 02:34 PM, Bastian Koppelmann wrote: > dvinit_hu/bu for ISA v1.3 calculate the higher part of the result, that is needed > for the overflow bits, after calculating the overflow bits. > > Signed-off-by: Bastian Koppelmann > --- > target-tricore/translate.c | 29 +++++++++++++++++------------ > 1 file changed, 17 insertions(+), 12 deletions(-) > > diff --git a/target-tricore/translate.c b/target-tricore/translate.c > index 0b7cf06..d3680c3 100644 > --- a/target-tricore/translate.c > +++ b/target-tricore/translate.c > @@ -6240,7 +6240,7 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) > uint32_t op2; > int r1, r2, r3; > > - TCGv temp, temp2; > + TCGv temp, temp2, temp3; > > op2 = MASK_OP_RR_OP2(ctx->opcode); > r3 = MASK_OP_RR_D(ctx->opcode); > @@ -6261,14 +6261,17 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) > case OPC2_32_RR_DVINIT_BU: > temp = tcg_temp_new(); > temp2 = tcg_temp_new(); > + temp3 = tcg_temp_new(); > + > + tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8); > /* reset av */ > tcg_gen_movi_tl(cpu_PSW_AV, 0); > if (!tricore_feature(env, TRICORE_FEATURE_131)) { > /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ > - tcg_gen_neg_tl(temp, cpu_gpr_d[r3+1]); > + tcg_gen_neg_tl(temp, temp3); > /* use cpu_PSW_AV to compare against 0 */ > - tcg_gen_movcond_tl(TCG_COND_LT, temp, cpu_gpr_d[r3+1], cpu_PSW_AV, > - temp, cpu_gpr_d[r3+1]); > + tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV, > + temp, temp3); > tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]); > tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV, > temp2, cpu_gpr_d[r2]); > @@ -6281,9 +6284,8 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) > /* sv */ > tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); > /* write result */ > - tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 8); > tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24); > - tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp); > + tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); > > tcg_temp_free(temp); > tcg_temp_free(temp2); > Mh, I forgot to free temp3 here. I'll change that after I applied it to my tricore-next branch. Cheers, Bastian