From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42523) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YaV00-0006bK-Ox for qemu-devel@nongnu.org; Tue, 24 Mar 2015 16:00:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YaUzv-00034V-Pt for qemu-devel@nongnu.org; Tue, 24 Mar 2015 16:00:28 -0400 Received: from mail-wg0-x233.google.com ([2a00:1450:400c:c00::233]:34230) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YaUzv-00034F-Je for qemu-devel@nongnu.org; Tue, 24 Mar 2015 16:00:23 -0400 Received: by wgs2 with SMTP id 2so3002181wgs.1 for ; Tue, 24 Mar 2015 13:00:22 -0700 (PDT) Sender: Paolo Bonzini Message-ID: <5511C251.8030907@redhat.com> Date: Tue, 24 Mar 2015 21:00:17 +0100 From: Paolo Bonzini MIME-Version: 1.0 References: <5511787F.40301@redhat.com> <55117DF5.7000408@redhat.com> <1355384493.3824166.1427214234629.JavaMail.zimbra@redhat.com> <5511A405.6090005@redhat.com> In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] RFC: memory API changes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Peter Crosthwaite , QEMU Developers , Greg Bellows , "Edgar E. Iglesias" , =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= , Richard Henderson On 24/03/2015 19:06, Peter Maydell wrote: > On 24 March 2015 at 17:51, Paolo Bonzini wrote: >> On 24/03/2015 17:35, Peter Maydell wrote: >>> On 24 March 2015 at 16:23, Paolo Bonzini wrote: >>>>> On 24 March 2015 at 15:08, Paolo Bonzini wrote: >>>> , for those callers >>>> of ld/st*_phys that use cs->as as the first argument. >>> >>> ...but I don't understand this caveat. I want to add arguments >>> and rename the functions for *all* callers of ld/st*_phys. >>> I don't want to specialcase the ones which happen to be >>> operating on cs->as. >> >> The ones that operate on cs->as could become (for some CPUs at least) >> special-cased accessors like the bus ones; for example building the >> MemTxAttrs according to internal CPU state. > > Sure, individual targets could do something like this if they > wanted (compare the arm_ldl_code functions), once these renames > have gone in. > >> ld/st*_phys actually started as CPU-specific accessors, and most uses >> are still of that kind, so it makes sense to me that we special-case >> them. Maybe it limits churn, maybe it doesn't. But if it doesn't, it's >> not like anything is lost. > > I think this is where we disagree. I see ld/st*_phys as being > really generic -- they take an AddressSpace, after all, and > part of the same family with address_space_read &c. If you > don't leave them as generic, then you end up having to use > the really awkward _read/_write for simple accesses and > then manage the byteswapping yourself. That's why I want > to rename them into address_space_* : to indicate that they > are all part of the same family, and you can use > address_space_read if you want to read an arbitrary byte > buffer, or address_space_ldl_be if you want to read a > big endian 32 bit word, and so on. I agree with that. I just want to keep ld/st*_phys _in addition_ as the short forms of address_space_ld/st*, and keep ld/st*_phys instead of address_space_ld/st* for those uses that have cs->as as the first argument. The rationale is to evolve ld/st*_phys into CPU-specific accessors paralleling the bus-specific accessors. Paolo > (The only reason they started out CPU specific is because > we didn't have any concept at all of having more than > one address space, so there wasn't any need to say which > one you meant when you were doing a load.) > > To me it makes much more sense that if a DMA controller > like pl080 wants to do an LE word read from the AS which > its bus master is connected to, that it can just do > word = ldl_le_phys(my_as, addr, ...); > > I'd expect pretty much any bus master to want to do this > kind of thing, in fact. It just happens that most of the > bus masters we have in QEMU right now are CPUs... > > -- PMM > >