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Date: Tue, 07 Apr 2015 15:18:02 +0200
From: Paolo Bonzini <pbonzini@redhat.com>
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Subject: Re: [Qemu-devel] target-i386: clear bsp bit when designating bsp
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To: =?windows-1252?Q?Andreas_F=E4rber?= <afaerber@suse.de>, qemu-devel@nongnu.org
Cc: Eduardo Habkost <ehabkost@redhat.com>, Nadav Amit <namit@cs.technion.ac.il>, mst@redhat.com, Igor Mammedov <imammedo@redhat.com>, nadav.amit@gmail.com, rth@twiddle.net



On 07/04/2015 13:57, Andreas F=E4rber wrote:
>> > If this is some issue with sync'ing state back and forth before QEMU=
 and
>> > KVM then the real issue has not been explained.
> Hm, hw/intc/apic_common.c:apic_reset_common() has:
>=20
>     bsp =3D cpu_is_bsp(s->cpu);
>     s->apicbase =3D APIC_DEFAULT_ADDRESS |
>         (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
>=20
> What this is doing is really:
>=20
>     bsp =3D cpu_get_apic_base(s->cpu->apic_state) & MSR_IA32_APICBASE_B=
SP;
>     s->apicbase =3D APIC_DEFAULT_ADDRESS |
>         (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
>=20
> Unless I'm missing something, since we are in the APIC device's reset
> function, this is effectively a twisted way of writing:
>=20
>     bsp =3D s->apicbase & MSR_IA32_APICBASE_BSP;
>     s->apicbase =3D APIC_DEFAULT_ADDRESS |
>         (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;

Yes, this is more readable.

> In which case we already relied on s->cpu and could thus simply change
> this to something like:
>=20
>     bsp =3D CPU(s->cpu)->cpu_index =3D=3D 0;
>     s->apicbase =3D APIC_DEFAULT_ADDRESS |
>         (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
>=20
> Then the apicbase manipulation would be nicely encapsulated in the APIC
> rather than the APIC reset retaining it and the CPU reset meddling with
> its state.

... but I find this worse.  apic_designate_bsp corresponds to hardware
executing the MP initialization protocol.

Paolo