From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49178) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yfnbr-00064T-7e for qemu-devel@nongnu.org; Wed, 08 Apr 2015 06:53:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yfnbp-0000Pt-DH for qemu-devel@nongnu.org; Wed, 08 Apr 2015 06:53:27 -0400 Received: from mail-wg0-x22e.google.com ([2a00:1450:400c:c00::22e]:33938) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yfnbp-0000Ph-3n for qemu-devel@nongnu.org; Wed, 08 Apr 2015 06:53:25 -0400 Received: by wgbdm7 with SMTP id dm7so84009069wgb.1 for ; Wed, 08 Apr 2015 03:53:24 -0700 (PDT) Sender: Paolo Bonzini Message-ID: <552508A1.7040804@redhat.com> Date: Wed, 08 Apr 2015 12:53:21 +0200 From: Paolo Bonzini MIME-Version: 1.0 References: <1428437400-8474-1-git-send-email-peter.maydell@linaro.org> <1428437400-8474-5-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1428437400-8474-5-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 04/14] Add MemTxAttrs to the IOTLB List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , qemu-devel@nongnu.org Cc: Peter Crosthwaite , patches@linaro.org, Greg Bellows , "Edgar E. Iglesias" , =?windows-1252?Q?Alex_Benn=E9e?= , Richard Henderson On 07/04/2015 22:09, Peter Maydell wrote: > Add a MemTxAttrs field to the IOTLB, and allow target-specific > code to set it via a new tlb_set_page_with_attrs() function; > pass the attributes through to the device when making IO accesses. > > Signed-off-by: Peter Maydell > --- > cputlb.c | 18 +++++++++++++++--- > include/exec/cpu-defs.h | 2 ++ > include/exec/exec-all.h | 3 +++ > softmmu_template.h | 4 ++-- > 4 files changed, 22 insertions(+), 5 deletions(-) > > diff --git a/cputlb.c b/cputlb.c > index 5e1cb8f..7606548 100644 > --- a/cputlb.c > +++ b/cputlb.c > @@ -249,9 +249,9 @@ static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr, > * Called from TCG-generated code, which is under an RCU read-side > * critical section. > */ > -void tlb_set_page(CPUState *cpu, target_ulong vaddr, > - hwaddr paddr, int prot, > - int mmu_idx, target_ulong size) > +void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, > + hwaddr paddr, MemTxAttrs attrs, int prot, > + int mmu_idx, target_ulong size) > { > CPUArchState *env = cpu->env_ptr; > MemoryRegionSection *section; > @@ -302,6 +302,7 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, > > /* refill the tlb */ > env->iotlb[mmu_idx][index].addr = iotlb - vaddr; > + env->iotlb[mmu_idx][index].attrs = attrs; > te->addend = addend - vaddr; > if (prot & PAGE_READ) { > te->addr_read = address; > @@ -331,6 +332,17 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, > } > } > > +/* Add a new TLB entry, but without specifying the memory > + * transaction attributes to be used. > + */ > +void tlb_set_page(CPUState *cpu, target_ulong vaddr, > + hwaddr paddr, int prot, > + int mmu_idx, target_ulong size) > +{ > + tlb_set_page_with_attrs(cpu, vaddr, paddr, MEMTXATTRS_UNSPECIFIED, > + prot, mmu_idx, size); > +} > + > /* NOTE: this function can trigger an exception */ > /* NOTE2: the returned address is not exactly the physical address: it > * is actually a ram_addr_t (in system mode; the user mode emulation > diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h > index 7f88185..3f56546 100644 > --- a/include/exec/cpu-defs.h > +++ b/include/exec/cpu-defs.h > @@ -30,6 +30,7 @@ > #ifndef CONFIG_USER_ONLY > #include "exec/hwaddr.h" > #endif > +#include "exec/memattrs.h" > > #ifndef TARGET_LONG_BITS > #error TARGET_LONG_BITS must be defined before including this header > @@ -109,6 +110,7 @@ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); > */ > typedef struct CPUIOTLBEntry { > hwaddr addr; > + MemTxAttrs attrs; > } CPUIOTLBEntry; > > #define CPU_COMMON_TLB \ > diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h > index ff1bc3e..b58cd47 100644 > --- a/include/exec/exec-all.h > +++ b/include/exec/exec-all.h > @@ -105,6 +105,9 @@ void tlb_flush(CPUState *cpu, int flush_global); > void tlb_set_page(CPUState *cpu, target_ulong vaddr, > hwaddr paddr, int prot, > int mmu_idx, target_ulong size); > +void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, > + hwaddr paddr, MemTxAttrs attrs, > + int prot, int mmu_idx, target_ulong size); > void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr); > #else > static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) > diff --git a/softmmu_template.h b/softmmu_template.h > index 7a36550..7310a93 100644 > --- a/softmmu_template.h > +++ b/softmmu_template.h > @@ -159,7 +159,7 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env, > } > > cpu->mem_io_vaddr = addr; > - io_mem_read(mr, physaddr, &val, 1 << SHIFT, MEMTXATTRS_UNSPECIFIED); > + io_mem_read(mr, physaddr, &val, 1 << SHIFT, iotlbentry->attrs); > return val; > } > #endif > @@ -380,7 +380,7 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env, > > cpu->mem_io_vaddr = addr; > cpu->mem_io_pc = retaddr; > - io_mem_write(mr, physaddr, val, 1 << SHIFT, MEMTXATTRS_UNSPECIFIED); > + io_mem_write(mr, physaddr, val, 1 << SHIFT, iotlbentry->attrs); > } > > void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, > Reviewed-by: Paolo Bonzini