From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52965) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YfnvV-0006wS-75 for qemu-devel@nongnu.org; Wed, 08 Apr 2015 07:13:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YfnvO-0000wl-NK for qemu-devel@nongnu.org; Wed, 08 Apr 2015 07:13:45 -0400 Received: from mail-wi0-x22a.google.com ([2a00:1450:400c:c05::22a]:38297) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YfnvO-0000wV-HW for qemu-devel@nongnu.org; Wed, 08 Apr 2015 07:13:38 -0400 Received: by wiun10 with SMTP id n10so53845194wiu.1 for ; Wed, 08 Apr 2015 04:13:37 -0700 (PDT) Sender: Paolo Bonzini Message-ID: <55250D5E.60508@redhat.com> Date: Wed, 08 Apr 2015 13:13:34 +0200 From: Paolo Bonzini MIME-Version: 1.0 References: <1428437400-8474-1-git-send-email-peter.maydell@linaro.org> <1428437400-8474-3-git-send-email-peter.maydell@linaro.org> <55250844.8080702@redhat.com> In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH 02/14] memory: Add MemTxAttrs, MemTxResult to io_mem_read and io_mem_write List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Peter Crosthwaite , Patch Tracking , QEMU Developers , Greg Bellows , "Edgar E. Iglesias" , =?UTF-8?B?QWxleCBCZW5uw6k=?= =?UTF-8?B?ZQ==?= , Richard Henderson On 08/04/2015 12:59, Peter Maydell wrote: > Incidentally in the course of this patch I noticed that we have > exactly two places outside the memory system that use these > functions: hw/s390x/s390-pci-inst.c and hw/vfio/pci.c. Is > this a reasonable thing, or should they in an ideal world > have created an AddressSpace to access things through? In the case of VFIO, I would just export pci_read/write_msix_table functions from the PCI core. In the case of s390 they would have to create an AddressSpace per BAR per device: the current code doesn't work for BARs backed by a RAM region, or with a complicated layout (aliases and the like). This reflects how s390 PCI is basically only used for VFIO, so it's passable: having a separate AddressSpace per BAR per device probably wouldn't scale too well. Paolo > (I have no opinion except that functions used in only one > or two places always look a little suspicious to me :-))