Re: [PATCH v5] riscv: Add support for the Zfa extension

[Richard Henderson <richard.henderson@linaro.org>]

On 6/30/23 13:52, Christoph Muellner wrote:
> +bool trans_fmvh_x_d(DisasContext *ctx, arg_fmvh_x_d *a)
> +{
> +    REQUIRE_FPU;
> +    REQUIRE_ZFA(ctx);
> +    REQUIRE_EXT(ctx, RVD);
> +    REQUIRE_32BIT(ctx);
> +
> +    TCGv dst = dest_gpr(ctx, a->rd);
> +    TCGv_i64 t1 = tcg_temp_new_i64();
> +
> +    tcg_gen_extract_i64(t1, cpu_fpr[a->rs1], 32, 32);
> +    tcg_gen_trunc_i64_tl(dst, t1);
> +    gen_set_gpr(ctx, a->rd, dst);

I think you would prefer

   tcg_gen_srai_tl(t1, cpu_fpr[rs1], 32);

so that dst is sign-extended to begin, instead of zero-extended.  You don't see an error 
because gen_set_gpr, for MXL_RV32, sign-extends the stored value.

However, the tcg optimizer would elide the second sign-extend if it can see that the value 
is already sign-extended.  So this could reduce to 1 operation instead of 2.


r~