From: Paolo Bonzini <pbonzini@redhat.com>
To: Gerd Hoffmann <kraxel@redhat.com>, qemu-devel@nongnu.org
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Subject: Re: [Qemu-devel] [PATCH 1/2] q35: implement SMRAM.D_LCK
Date: Tue, 14 Apr 2015 16:35:10 +0200 [thread overview]
Message-ID: <552D259E.405@redhat.com> (raw)
In-Reply-To: <1429017160-3583-1-git-send-email-kraxel@redhat.com>
On 14/04/2015 15:12, Gerd Hoffmann wrote:
> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
> ---
> hw/pci-host/q35.c | 17 ++++++++++++++++-
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
> index 79bab15..9227489 100644
> --- a/hw/pci-host/q35.c
> +++ b/hw/pci-host/q35.c
> @@ -268,6 +268,20 @@ static void mch_update_smram(MCHPCIState *mch)
> PCIDevice *pd = PCI_DEVICE(mch);
> bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME);
>
> + /* implement SMRAM.D_LCK */
> + if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) {
> + pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN;
> +
> + pd->wmask[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN;
> + pd->wmask[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_LCK;
> + pd->wmask[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_G_SMRAME;
> + pd->wmask[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG_MASK;
> +
> + pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] &= ~MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME;
> + pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] &= ~MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK;
> + pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] &= ~MCH_HOST_BRIDGE_ESMRAMC_T_EN;
> + }
> +
> memory_region_transaction_begin();
>
> if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) {
> @@ -297,7 +311,6 @@ static void mch_write_config(PCIDevice *d,
> {
> MCHPCIState *mch = MCH_PCI_DEVICE(d);
>
> - /* XXX: implement SMRAM.D_LOCK */
> pci_default_write_config(d, address, val, len);
>
> if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0,
> @@ -351,6 +364,8 @@ static void mch_reset(DeviceState *qdev)
> MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
>
> d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
> + d->wmask[MCH_HOST_BRIDGE_SMRAM] = 0xff;
> + d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = 0xff;
S3, if I remember correctly, should not be able to reset D_LCK. Does
this do the right thing?
Paolo
>
> mch_update(mch);
> }
>
next prev parent reply other threads:[~2015-04-14 14:35 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-14 13:12 [Qemu-devel] [PATCH 1/2] q35: implement SMRAM.D_LCK Gerd Hoffmann
2015-04-14 13:12 ` [Qemu-devel] [PATCH 2/2] q35: add test for SMRAM.D_LCK Gerd Hoffmann
2015-04-14 14:35 ` Paolo Bonzini [this message]
2015-04-15 13:58 ` [Qemu-devel] [PATCH 1/2] q35: implement SMRAM.D_LCK Gerd Hoffmann
2015-04-16 8:12 ` Paolo Bonzini
2015-04-18 21:08 ` Laszlo Ersek
2015-04-14 15:41 ` Michael S. Tsirkin
2015-04-14 15:51 ` Michael S. Tsirkin
2015-04-15 14:12 ` Gerd Hoffmann
2015-04-16 8:05 ` Michael S. Tsirkin
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