From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35668) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yi1vr-00033K-Er for qemu-devel@nongnu.org; Tue, 14 Apr 2015 10:35:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yi1vn-0001xg-Cz for qemu-devel@nongnu.org; Tue, 14 Apr 2015 10:35:19 -0400 Received: from mail-wi0-x231.google.com ([2a00:1450:400c:c05::231]:38093) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yi1vn-0001xV-5j for qemu-devel@nongnu.org; Tue, 14 Apr 2015 10:35:15 -0400 Received: by wiun10 with SMTP id n10so24387036wiu.1 for ; Tue, 14 Apr 2015 07:35:14 -0700 (PDT) Sender: Paolo Bonzini Message-ID: <552D259E.405@redhat.com> Date: Tue, 14 Apr 2015 16:35:10 +0200 From: Paolo Bonzini MIME-Version: 1.0 References: <1429017160-3583-1-git-send-email-kraxel@redhat.com> In-Reply-To: <1429017160-3583-1-git-send-email-kraxel@redhat.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 1/2] q35: implement SMRAM.D_LCK List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Gerd Hoffmann , qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" On 14/04/2015 15:12, Gerd Hoffmann wrote: > Signed-off-by: Gerd Hoffmann > --- > hw/pci-host/q35.c | 17 ++++++++++++++++- > 1 file changed, 16 insertions(+), 1 deletion(-) > > diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c > index 79bab15..9227489 100644 > --- a/hw/pci-host/q35.c > +++ b/hw/pci-host/q35.c > @@ -268,6 +268,20 @@ static void mch_update_smram(MCHPCIState *mch) > PCIDevice *pd = PCI_DEVICE(mch); > bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME); > > + /* implement SMRAM.D_LCK */ > + if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) { > + pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; > + > + pd->wmask[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; > + pd->wmask[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_LCK; > + pd->wmask[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_G_SMRAME; > + pd->wmask[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG_MASK; > + > + pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] &= ~MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME; > + pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] &= ~MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK; > + pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] &= ~MCH_HOST_BRIDGE_ESMRAMC_T_EN; > + } > + > memory_region_transaction_begin(); > > if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) { > @@ -297,7 +311,6 @@ static void mch_write_config(PCIDevice *d, > { > MCHPCIState *mch = MCH_PCI_DEVICE(d); > > - /* XXX: implement SMRAM.D_LOCK */ > pci_default_write_config(d, address, val, len); > > if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, > @@ -351,6 +364,8 @@ static void mch_reset(DeviceState *qdev) > MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); > > d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; > + d->wmask[MCH_HOST_BRIDGE_SMRAM] = 0xff; > + d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = 0xff; S3, if I remember correctly, should not be able to reset D_LCK. Does this do the right thing? Paolo > > mch_update(mch); > } >