* [PATCH v17 01/13] linux-user: Add LoongArch generic header files
2022-06-16 12:15 [PATCH v17 00/13] Add LoongArch linux-user emulation support Song Gao
@ 2022-06-16 12:15 ` Song Gao
2022-06-16 12:16 ` [PATCH v17 02/13] linux-user: Add LoongArch signal support Song Gao
` (11 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Song Gao @ 2022-06-16 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, laurent, gaosong, Xiaojuan Yang,
Philippe Mathieu-Daudé, WANG Xuerui
This includes:
- sockbits.h
- target_errno_defs.h
- target_fcntl.h
- termbits.h
- target_resource.h
- target_structs.h
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: WANG Xuerui <git@xen0n.name>
---
linux-user/loongarch64/sockbits.h | 11 +++++++++++
linux-user/loongarch64/target_errno_defs.h | 12 ++++++++++++
linux-user/loongarch64/target_fcntl.h | 11 +++++++++++
linux-user/loongarch64/target_prctl.h | 1 +
linux-user/loongarch64/target_resource.h | 11 +++++++++++
linux-user/loongarch64/target_structs.h | 11 +++++++++++
linux-user/loongarch64/termbits.h | 11 +++++++++++
7 files changed, 68 insertions(+)
create mode 100644 linux-user/loongarch64/sockbits.h
create mode 100644 linux-user/loongarch64/target_errno_defs.h
create mode 100644 linux-user/loongarch64/target_fcntl.h
create mode 100644 linux-user/loongarch64/target_prctl.h
create mode 100644 linux-user/loongarch64/target_resource.h
create mode 100644 linux-user/loongarch64/target_structs.h
create mode 100644 linux-user/loongarch64/termbits.h
diff --git a/linux-user/loongarch64/sockbits.h b/linux-user/loongarch64/sockbits.h
new file mode 100644
index 0000000000..1cffcae120
--- /dev/null
+++ b/linux-user/loongarch64/sockbits.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef LOONGARCH_TARGET_SOCKBITS_H
+#define LOONGARCH_TARGET_SOCKBITS_H
+
+#include "../generic/sockbits.h"
+
+#endif
diff --git a/linux-user/loongarch64/target_errno_defs.h b/linux-user/loongarch64/target_errno_defs.h
new file mode 100644
index 0000000000..c198b8aca9
--- /dev/null
+++ b/linux-user/loongarch64/target_errno_defs.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef LOONGARCH_TARGET_ERRNO_DEFS_H
+#define LOONGARCH_TARGET_ERRNO_DEFS_H
+
+/* Target uses generic errno */
+#include "../generic/target_errno_defs.h"
+
+#endif
diff --git a/linux-user/loongarch64/target_fcntl.h b/linux-user/loongarch64/target_fcntl.h
new file mode 100644
index 0000000000..99bf586854
--- /dev/null
+++ b/linux-user/loongarch64/target_fcntl.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef LOONGARCH_TARGET_FCNTL_H
+#define LOONGARCH_TARGET_FCNTL_H
+
+#include "../generic/fcntl.h"
+
+#endif
diff --git a/linux-user/loongarch64/target_prctl.h b/linux-user/loongarch64/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/loongarch64/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/loongarch64/target_resource.h b/linux-user/loongarch64/target_resource.h
new file mode 100644
index 0000000000..0f86bf24ee
--- /dev/null
+++ b/linux-user/loongarch64/target_resource.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef LOONGARCH_TARGET_RESOURCE_H
+#define LOONGARCH_TARGET_RESOURCE_H
+
+#include "../generic/target_resource.h"
+
+#endif
diff --git a/linux-user/loongarch64/target_structs.h b/linux-user/loongarch64/target_structs.h
new file mode 100644
index 0000000000..6041441e15
--- /dev/null
+++ b/linux-user/loongarch64/target_structs.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef LOONGARCH_TARGET_STRUCTS_H
+#define LOONGARCH_TARGET_STRUCTS_H
+
+#include "../generic/target_structs.h"
+
+#endif
diff --git a/linux-user/loongarch64/termbits.h b/linux-user/loongarch64/termbits.h
new file mode 100644
index 0000000000..d425db8748
--- /dev/null
+++ b/linux-user/loongarch64/termbits.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef LOONGARCH_TARGET_TERMBITS_H
+#define LOONGARCH_TARGET_TERMBITS_H
+
+#include "../generic/termbits.h"
+
+#endif
--
2.31.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v17 02/13] linux-user: Add LoongArch signal support
2022-06-16 12:15 [PATCH v17 00/13] Add LoongArch linux-user emulation support Song Gao
2022-06-16 12:15 ` [PATCH v17 01/13] linux-user: Add LoongArch generic header files Song Gao
@ 2022-06-16 12:16 ` Song Gao
2022-06-18 2:47 ` Richard Henderson
2022-06-16 12:16 ` [PATCH v17 03/13] linux-user: Add LoongArch elf support Song Gao
` (10 subsequent siblings)
12 siblings, 1 reply; 20+ messages in thread
From: Song Gao @ 2022-06-16 12:16 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson, laurent, gaosong, Xiaojuan Yang
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
---
linux-user/loongarch64/signal.c | 312 +++++++++++++++++++++++++
linux-user/loongarch64/target_signal.h | 13 ++
2 files changed, 325 insertions(+)
create mode 100644 linux-user/loongarch64/signal.c
create mode 100644 linux-user/loongarch64/target_signal.h
diff --git a/linux-user/loongarch64/signal.c b/linux-user/loongarch64/signal.c
new file mode 100644
index 0000000000..e291d72f85
--- /dev/null
+++ b/linux-user/loongarch64/signal.c
@@ -0,0 +1,312 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * LoongArch emulation of Linux signals
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "qemu.h"
+#include "user-internals.h"
+#include "signal-common.h"
+#include "linux-user/trace.h"
+
+#include "target/loongarch/internals.h"
+
+/* FP context was used */
+#define SC_USED_FP (1 << 0)
+
+struct target_sigcontext {
+ uint64_t sc_pc;
+ uint64_t sc_regs[32];
+ uint32_t sc_flags;
+ uint64_t sc_extcontext[0] __attribute__((aligned(16)));
+};
+
+struct target_fpu_context {
+ uint64_t regs[32];
+ uint64_t fcc;
+ uint32_t fcsr;
+};
+
+struct target_sctx_info {
+ uint32_t magic;
+ uint32_t size;
+ uint64_t padding; /* padding to 16 bytes */
+};
+
+struct target_ucontext {
+ target_ulong tuc_flags;
+ struct target_ucontext *tuc_link;
+ target_stack_t tuc_stack;
+ target_sigset_t tuc_sigmask;
+ uint8_t __unused[1024 / 8 - sizeof(target_sigset_t)];
+ struct target_sigcontext tuc_mcontext;
+};
+
+struct target_rt_sigframe {
+ struct target_siginfo rs_info;
+ struct target_ucontext rs_uc;
+};
+
+struct ctx_layout {
+ abi_ulong addr;
+ unsigned int size;
+};
+
+struct extctx_layout {
+ unsigned int size;
+ unsigned int flags;
+ struct ctx_layout fpu;
+ struct ctx_layout end;
+};
+
+static uint64_t read_all_fcc(CPULoongArchState *env)
+{
+ uint64_t ret = 0;
+
+ for (int i = 0; i < 8; ++i) {
+ ret |= (uint64_t)env->cf[i] << (i * 8);
+ }
+
+ return ret;
+}
+
+static void write_all_fcc(CPULoongArchState *env, uint64_t val)
+{
+ for (int i = 0; i < 8; ++i) {
+ env->cf[i] = (val >> (i * 8)) & 1;
+ }
+}
+
+static void *get_ctx(struct target_sctx_info *info)
+{
+ return (char *)info + sizeof(struct target_sctx_info);
+}
+
+static void copy_fpu_to_sigcontext(CPULoongArchState *env,
+ struct extctx_layout *extctx)
+{
+ int i;
+ struct target_sctx_info *info = (struct target_sctx_info *)extctx->fpu.addr;
+ struct target_fpu_context *fpu_ctx = get_ctx(info);
+
+ for (i = 1; i < 32; ++i) {
+ __put_user(env->fpr[i], &fpu_ctx->regs[i]);
+ }
+
+ fpu_ctx->fcc = read_all_fcc(env);
+ __put_user(env->fcsr0, &fpu_ctx->fcsr);
+ __put_user(extctx->fpu.size, &info->size);
+}
+
+static abi_ulong extframe_alloc(struct extctx_layout *extctx,
+ struct ctx_layout *layout,
+ size_t size, abi_ulong base)
+{
+ abi_ulong new_base = base - size;
+
+ new_base -= sizeof(struct target_sctx_info);
+ layout->addr = new_base;
+ layout->size = (unsigned int)(base - new_base);
+ extctx->size += layout->size;
+
+ return new_base;
+}
+
+static abi_ulong setup_extcontext(struct extctx_layout *extctx, abi_ulong sp)
+{
+ abi_ulong new_sp = sp;
+
+ memset(extctx, 0, sizeof(struct extctx_layout));
+ new_sp -= sizeof(struct target_sctx_info);
+
+ extctx->end.addr = new_sp;
+ extctx->end.size = (unsigned int)sizeof(struct target_sctx_info);
+ extctx->size += extctx->end.size;
+ extctx->flags = SC_USED_FP;
+
+ new_sp = extframe_alloc(extctx, &extctx->fpu,
+ sizeof(struct target_fpu_context), new_sp);
+
+ return new_sp;
+}
+
+static void setup_sigcontext(CPULoongArchState *env,
+ struct target_sigcontext *sc,
+ struct extctx_layout *extctx)
+{
+ int i;
+
+ __put_user(extctx->flags, &sc->sc_flags);
+ __put_user(env->pc, &sc->sc_pc);
+
+ for (i = 1; i < 32; ++i) {
+ __put_user(env->gpr[i], &sc->sc_regs[i]);
+ }
+
+ copy_fpu_to_sigcontext(env, extctx);
+}
+
+static void copy_fpu_from_sigcontext(CPULoongArchState *env,
+ struct extctx_layout *extctx)
+{
+ int i;
+ struct target_sctx_info *info = (struct target_sctx_info *)extctx->fpu.addr;
+ struct target_fpu_context *fpu_ctx = get_ctx(info);
+
+ for (i = 1; i < 32; ++i) {
+ __get_user(env->fpr[i], &fpu_ctx->regs[i]);
+ }
+ write_all_fcc(env, fpu_ctx->fcc);
+ __get_user(env->fcsr0, &fpu_ctx->fcsr);
+}
+
+static int parse_extcontext(struct target_sigcontext *sc,
+ struct extctx_layout *extctx)
+{
+ unsigned int size;
+ struct target_sctx_info *info = (struct target_sctx_info *)
+ &sc->sc_extcontext;
+
+ __get_user(size, &info->size);
+
+ if (size < (sizeof(struct target_sctx_info) +
+ sizeof(struct target_fpu_context))) {
+ return -TARGET_EINVAL;
+ }
+
+ extctx->fpu.addr = (abi_ulong)info;
+ info = (struct target_sctx_info *)((char *)info + size);
+
+ return 0;
+}
+
+static int restore_sigcontext(CPULoongArchState *env,
+ struct target_sigcontext *sc)
+{
+ int i;
+ int ret = 0;
+ struct extctx_layout extctx;
+
+ memset(&extctx, 0, sizeof(struct extctx_layout));
+
+ __get_user(extctx.flags, &sc->sc_flags);
+
+ ret = parse_extcontext(sc, &extctx);
+ if (ret < 0) {
+ goto bad;
+ }
+
+ __get_user(env->pc, &sc->sc_pc);
+ for (i = 1; i < 32; ++i) {
+ __get_user(env->gpr[i], &sc->sc_regs[i]);
+ }
+
+ copy_fpu_from_sigcontext(env, &extctx);
+ restore_fp_status(env);
+
+bad:
+ return ret;
+}
+
+/*
+ * Determine which stack to use.
+ */
+static abi_ulong get_sigframe(struct target_sigaction *ka,
+ CPULoongArchState *env, size_t frame_size,
+ struct extctx_layout *extctx)
+{
+ abi_ulong sp;
+
+ sp = target_sigsp(get_sp_from_cpustate(env) - 32, ka);
+ sp = setup_extcontext(extctx, sp);
+
+ return (sp - frame_size) & ~15;
+}
+
+void setup_rt_frame(int sig, struct target_sigaction *ka,
+ target_siginfo_t *info,
+ target_sigset_t *set, CPULoongArchState *env)
+{
+ struct target_rt_sigframe *frame;
+ struct extctx_layout extctx;
+ abi_ulong frame_addr;
+ int i;
+
+ frame_addr = get_sigframe(ka, env, sizeof(*frame), &extctx);
+ trace_user_setup_rt_frame(env, frame_addr);
+ if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) {
+ goto give_sigsegv;
+ }
+
+ tswap_siginfo(&frame->rs_info, info);
+
+ __put_user(0, &frame->rs_uc.tuc_flags);
+ __put_user(0, &frame->rs_uc.tuc_link);
+ target_save_altstack(&frame->rs_uc.tuc_stack, env);
+
+ setup_sigcontext(env, &frame->rs_uc.tuc_mcontext, &extctx);
+
+ for (i = 0; i < TARGET_NSIG_WORDS; i++) {
+ __put_user(set->sig[i], &frame->rs_uc.tuc_sigmask.sig[i]);
+ }
+
+ env->gpr[4] = sig;
+ env->gpr[5] = frame_addr + offsetof(struct target_rt_sigframe, rs_info);
+ env->gpr[6] = frame_addr + offsetof(struct target_rt_sigframe, rs_uc);
+ env->gpr[3] = frame_addr;
+ env->gpr[1] = default_rt_sigreturn;
+
+ env->pc = ka->_sa_handler;
+ unlock_user_struct(frame, frame_addr, 1);
+ return;
+
+give_sigsegv:
+ unlock_user_struct(frame, frame_addr, 1);
+ force_sigsegv(sig);
+}
+
+long do_rt_sigreturn(CPULoongArchState *env)
+{
+ int ret = 0;
+ struct target_rt_sigframe *frame;
+ abi_ulong frame_addr;
+ sigset_t blocked;
+
+ frame_addr = env->gpr[3];
+ trace_user_do_rt_sigreturn(env, frame_addr);
+ if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1)) {
+ goto badframe;
+ }
+
+ target_to_host_sigset(&blocked, &frame->rs_uc.tuc_sigmask);
+ set_sigmask(&blocked);
+
+ ret = restore_sigcontext(env, &frame->rs_uc.tuc_mcontext);
+ if (ret < 0) {
+ goto badframe;
+ }
+
+ target_restore_altstack(&frame->rs_uc.tuc_stack, env);
+
+ unlock_user_struct(frame, frame_addr, 0);
+ return -QEMU_ESIGRETURN;
+
+badframe:
+ unlock_user_struct(frame, frame_addr, 0);
+ force_sig(TARGET_SIGSEGV);
+ return -QEMU_ESIGRETURN;
+}
+
+void setup_sigtramp(abi_ulong sigtramp_page)
+{
+ uint32_t *tramp = lock_user(VERIFY_WRITE, sigtramp_page, 8, 0);
+ assert(tramp != NULL);
+
+ __put_user(0x03822c0b, tramp + 0); /* ori a7, zero, 0x8b */
+ __put_user(0x002b0000, tramp + 1); /* syscall 0 */
+
+ default_rt_sigreturn = sigtramp_page;
+ unlock_user(tramp, sigtramp_page, 8);
+}
diff --git a/linux-user/loongarch64/target_signal.h b/linux-user/loongarch64/target_signal.h
new file mode 100644
index 0000000000..ad3aaffcb4
--- /dev/null
+++ b/linux-user/loongarch64/target_signal.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef LOONGARCH_TARGET_SIGNAL_H
+#define LOONGARCH_TARGET_SIGNAL_H
+
+#include "../generic/signal.h"
+
+#define TARGET_ARCH_HAS_SIGTRAMP_PAGE 1
+
+#endif /* LOONGARCH_TARGET_SIGNAL_H */
--
2.31.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v17 02/13] linux-user: Add LoongArch signal support
2022-06-16 12:16 ` [PATCH v17 02/13] linux-user: Add LoongArch signal support Song Gao
@ 2022-06-18 2:47 ` Richard Henderson
0 siblings, 0 replies; 20+ messages in thread
From: Richard Henderson @ 2022-06-18 2:47 UTC (permalink / raw)
To: Song Gao, qemu-devel; +Cc: laurent, Xiaojuan Yang
On 6/16/22 05:16, Song Gao wrote:
> +static void copy_fpu_to_sigcontext(CPULoongArchState *env,
> + struct extctx_layout *extctx)
> +{
> + int i;
> + struct target_sctx_info *info = (struct target_sctx_info *)extctx->fpu.addr;
> + struct target_fpu_context *fpu_ctx = get_ctx(info);
> +
> + for (i = 1; i < 32; ++i) {
> + __put_user(env->fpr[i], &fpu_ctx->regs[i]);
> + }
> +
> + fpu_ctx->fcc = read_all_fcc(env);
> + __put_user(env->fcsr0, &fpu_ctx->fcsr);
> + __put_user(extctx->fpu.size, &info->size);
> +}
You've failed to set magic.
> +
> +static abi_ulong extframe_alloc(struct extctx_layout *extctx,
> + struct ctx_layout *layout,
> + size_t size, abi_ulong base)
> +{
> + abi_ulong new_base = base - size;
> +
> + new_base -= sizeof(struct target_sctx_info);
Missing ROUND_DOWN.
> + layout->addr = new_base;
> + layout->size = (unsigned int)(base - new_base);
Cast not required.
> +static int parse_extcontext(struct target_sigcontext *sc,
> + struct extctx_layout *extctx)
> +{
> + unsigned int size;
> + struct target_sctx_info *info = (struct target_sctx_info *)
> + &sc->sc_extcontext;
> +
> + __get_user(size, &info->size);
> +
> + if (size < (sizeof(struct target_sctx_info) +
> + sizeof(struct target_fpu_context))) {
> + return -TARGET_EINVAL;
> + }
> +
> + extctx->fpu.addr = (abi_ulong)info;
> + info = (struct target_sctx_info *)((char *)info + size);
> +
> + return 0;
> +}
This does not even closely resemble the kernel's parse_extcontext.
You *really* have to be more careful about this.
r~
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v17 03/13] linux-user: Add LoongArch elf support
2022-06-16 12:15 [PATCH v17 00/13] Add LoongArch linux-user emulation support Song Gao
2022-06-16 12:15 ` [PATCH v17 01/13] linux-user: Add LoongArch generic header files Song Gao
2022-06-16 12:16 ` [PATCH v17 02/13] linux-user: Add LoongArch signal support Song Gao
@ 2022-06-16 12:16 ` Song Gao
2022-06-16 12:16 ` [PATCH v17 04/13] linux-user: Add LoongArch syscall support Song Gao
` (9 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Song Gao @ 2022-06-16 12:16 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, laurent, gaosong, Xiaojuan Yang,
Philippe Mathieu-Daudé
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
linux-user/elfload.c | 91 +++++++++++++++++++++++++++++
linux-user/loongarch64/target_elf.h | 12 ++++
2 files changed, 103 insertions(+)
create mode 100644 linux-user/loongarch64/target_elf.h
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index f7eae357f4..7351d0e089 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -918,6 +918,97 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUPPCState *en
#endif
+#ifdef TARGET_LOONGARCH64
+
+#define ELF_START_MMAP 0x80000000
+
+#define ELF_CLASS ELFCLASS64
+#define ELF_ARCH EM_LOONGARCH
+
+#define elf_check_arch(x) ((x) == EM_LOONGARCH)
+
+static inline void init_thread(struct target_pt_regs *regs,
+ struct image_info *infop)
+{
+ /*Set crmd PG,DA = 1,0 */
+ regs->csr.crmd = 2 << 3;
+ regs->csr.era = infop->entry;
+ regs->regs[3] = infop->start_stack;
+}
+
+/* See linux kernel: arch/loongarch/include/asm/elf.h */
+#define ELF_NREG 45
+typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG];
+
+enum {
+ TARGET_EF_R0 = 0,
+ TARGET_EF_CSR_ERA = TARGET_EF_R0 + 33,
+ TARGET_EF_CSR_BADV = TARGET_EF_R0 + 34,
+};
+
+static void elf_core_copy_regs(target_elf_gregset_t *regs,
+ const CPULoongArchState *env)
+{
+ int i;
+
+ (*regs)[TARGET_EF_R0] = 0;
+
+ for (i = 1; i < ARRAY_SIZE(env->gpr); i++) {
+ (*regs)[TARGET_EF_R0 + i] = tswapreg(env->gpr[i]);
+ }
+
+ (*regs)[TARGET_EF_CSR_ERA] = tswapreg(env->pc);
+ (*regs)[TARGET_EF_CSR_BADV] = tswapreg(env->CSR_BADV);
+}
+
+#define USE_ELF_CORE_DUMP
+#define ELF_EXEC_PAGESIZE 4096
+
+#define ELF_HWCAP get_elf_hwcap()
+
+/* See arch/loongarch/include/uapi/asm/hwcap.h */
+enum {
+ HWCAP_LOONGARCH_CPUCFG = (1 << 0),
+ HWCAP_LOONGARCH_LAM = (1 << 1),
+ HWCAP_LOONGARCH_UAL = (1 << 2),
+ HWCAP_LOONGARCH_FPU = (1 << 3),
+ HWCAP_LOONGARCH_LSX = (1 << 4),
+ HWCAP_LOONGARCH_LASX = (1 << 5),
+ HWCAP_LOONGARCH_CRC32 = (1 << 6),
+ HWCAP_LOONGARCH_COMPLEX = (1 << 7),
+ HWCAP_LOONGARCH_CRYPTO = (1 << 8),
+ HWCAP_LOONGARCH_LVZ = (1 << 9),
+ HWCAP_LOONGARCH_LBT_X86 = (1 << 10),
+ HWCAP_LOONGARCH_LBT_ARM = (1 << 11),
+ HWCAP_LOONGARCH_LBT_MIPS = (1 << 12),
+};
+
+static uint32_t get_elf_hwcap(void)
+{
+ LoongArchCPU *cpu = LOONGARCH_CPU(thread_cpu);
+ uint32_t hwcaps = 0;
+
+ hwcaps |= HWCAP_LOONGARCH_CRC32;
+
+ if (FIELD_EX32(cpu->env.cpucfg[1], CPUCFG1, UAL)) {
+ hwcaps |= HWCAP_LOONGARCH_UAL;
+ }
+
+ if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, FP)) {
+ hwcaps |= HWCAP_LOONGARCH_FPU;
+ }
+
+ if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LAM)) {
+ hwcaps |= HWCAP_LOONGARCH_LAM;
+ }
+
+ return hwcaps;
+}
+
+#define ELF_PLATFORM "loongarch"
+
+#endif /* TARGET_LOONGARCH64 */
+
#ifdef TARGET_MIPS
#define ELF_START_MMAP 0x80000000
diff --git a/linux-user/loongarch64/target_elf.h b/linux-user/loongarch64/target_elf.h
new file mode 100644
index 0000000000..95c3f05a46
--- /dev/null
+++ b/linux-user/loongarch64/target_elf.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef LOONGARCH_TARGET_ELF_H
+#define LOONGARCH_TARGET_ELF_H
+static inline const char *cpu_get_model(uint32_t eflags)
+{
+ return "la464";
+}
+#endif
--
2.31.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v17 04/13] linux-user: Add LoongArch syscall support
2022-06-16 12:15 [PATCH v17 00/13] Add LoongArch linux-user emulation support Song Gao
` (2 preceding siblings ...)
2022-06-16 12:16 ` [PATCH v17 03/13] linux-user: Add LoongArch elf support Song Gao
@ 2022-06-16 12:16 ` Song Gao
2022-06-16 12:16 ` [PATCH v17 05/13] linux-user: Add LoongArch cpu_loop support Song Gao
` (8 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Song Gao @ 2022-06-16 12:16 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, laurent, gaosong, Xiaojuan Yang,
Philippe Mathieu-Daudé
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
linux-user/loongarch64/syscall_nr.h | 312 ++++++++++++++++++++++++
linux-user/loongarch64/target_syscall.h | 48 ++++
linux-user/syscall_defs.h | 6 +-
scripts/gensyscalls.sh | 2 +
4 files changed, 367 insertions(+), 1 deletion(-)
create mode 100644 linux-user/loongarch64/syscall_nr.h
create mode 100644 linux-user/loongarch64/target_syscall.h
diff --git a/linux-user/loongarch64/syscall_nr.h b/linux-user/loongarch64/syscall_nr.h
new file mode 100644
index 0000000000..be00915adf
--- /dev/null
+++ b/linux-user/loongarch64/syscall_nr.h
@@ -0,0 +1,312 @@
+/*
+ * This file contains the system call numbers.
+ * Do not modify.
+ * This file is generated by scripts/gensyscalls.sh
+ */
+#ifndef LINUX_USER_LOONGARCH_SYSCALL_NR_H
+#define LINUX_USER_LOONGARCH_SYSCALL_NR_H
+
+#define TARGET_NR_io_setup 0
+#define TARGET_NR_io_destroy 1
+#define TARGET_NR_io_submit 2
+#define TARGET_NR_io_cancel 3
+#define TARGET_NR_io_getevents 4
+#define TARGET_NR_setxattr 5
+#define TARGET_NR_lsetxattr 6
+#define TARGET_NR_fsetxattr 7
+#define TARGET_NR_getxattr 8
+#define TARGET_NR_lgetxattr 9
+#define TARGET_NR_fgetxattr 10
+#define TARGET_NR_listxattr 11
+#define TARGET_NR_llistxattr 12
+#define TARGET_NR_flistxattr 13
+#define TARGET_NR_removexattr 14
+#define TARGET_NR_lremovexattr 15
+#define TARGET_NR_fremovexattr 16
+#define TARGET_NR_getcwd 17
+#define TARGET_NR_lookup_dcookie 18
+#define TARGET_NR_eventfd2 19
+#define TARGET_NR_epoll_create1 20
+#define TARGET_NR_epoll_ctl 21
+#define TARGET_NR_epoll_pwait 22
+#define TARGET_NR_dup 23
+#define TARGET_NR_dup3 24
+#define TARGET_NR_fcntl 25
+#define TARGET_NR_inotify_init1 26
+#define TARGET_NR_inotify_add_watch 27
+#define TARGET_NR_inotify_rm_watch 28
+#define TARGET_NR_ioctl 29
+#define TARGET_NR_ioprio_set 30
+#define TARGET_NR_ioprio_get 31
+#define TARGET_NR_flock 32
+#define TARGET_NR_mknodat 33
+#define TARGET_NR_mkdirat 34
+#define TARGET_NR_unlinkat 35
+#define TARGET_NR_symlinkat 36
+#define TARGET_NR_linkat 37
+#define TARGET_NR_umount2 39
+#define TARGET_NR_mount 40
+#define TARGET_NR_pivot_root 41
+#define TARGET_NR_nfsservctl 42
+#define TARGET_NR_statfs 43
+#define TARGET_NR_fstatfs 44
+#define TARGET_NR_truncate 45
+#define TARGET_NR_ftruncate 46
+#define TARGET_NR_fallocate 47
+#define TARGET_NR_faccessat 48
+#define TARGET_NR_chdir 49
+#define TARGET_NR_fchdir 50
+#define TARGET_NR_chroot 51
+#define TARGET_NR_fchmod 52
+#define TARGET_NR_fchmodat 53
+#define TARGET_NR_fchownat 54
+#define TARGET_NR_fchown 55
+#define TARGET_NR_openat 56
+#define TARGET_NR_close 57
+#define TARGET_NR_vhangup 58
+#define TARGET_NR_pipe2 59
+#define TARGET_NR_quotactl 60
+#define TARGET_NR_getdents64 61
+#define TARGET_NR_lseek 62
+#define TARGET_NR_read 63
+#define TARGET_NR_write 64
+#define TARGET_NR_readv 65
+#define TARGET_NR_writev 66
+#define TARGET_NR_pread64 67
+#define TARGET_NR_pwrite64 68
+#define TARGET_NR_preadv 69
+#define TARGET_NR_pwritev 70
+#define TARGET_NR_sendfile 71
+#define TARGET_NR_pselect6 72
+#define TARGET_NR_ppoll 73
+#define TARGET_NR_signalfd4 74
+#define TARGET_NR_vmsplice 75
+#define TARGET_NR_splice 76
+#define TARGET_NR_tee 77
+#define TARGET_NR_readlinkat 78
+#define TARGET_NR_sync 81
+#define TARGET_NR_fsync 82
+#define TARGET_NR_fdatasync 83
+#define TARGET_NR_sync_file_range 84
+#define TARGET_NR_timerfd_create 85
+#define TARGET_NR_timerfd_settime 86
+#define TARGET_NR_timerfd_gettime 87
+#define TARGET_NR_utimensat 88
+#define TARGET_NR_acct 89
+#define TARGET_NR_capget 90
+#define TARGET_NR_capset 91
+#define TARGET_NR_personality 92
+#define TARGET_NR_exit 93
+#define TARGET_NR_exit_group 94
+#define TARGET_NR_waitid 95
+#define TARGET_NR_set_tid_address 96
+#define TARGET_NR_unshare 97
+#define TARGET_NR_futex 98
+#define TARGET_NR_set_robust_list 99
+#define TARGET_NR_get_robust_list 100
+#define TARGET_NR_nanosleep 101
+#define TARGET_NR_getitimer 102
+#define TARGET_NR_setitimer 103
+#define TARGET_NR_kexec_load 104
+#define TARGET_NR_init_module 105
+#define TARGET_NR_delete_module 106
+#define TARGET_NR_timer_create 107
+#define TARGET_NR_timer_gettime 108
+#define TARGET_NR_timer_getoverrun 109
+#define TARGET_NR_timer_settime 110
+#define TARGET_NR_timer_delete 111
+#define TARGET_NR_clock_settime 112
+#define TARGET_NR_clock_gettime 113
+#define TARGET_NR_clock_getres 114
+#define TARGET_NR_clock_nanosleep 115
+#define TARGET_NR_syslog 116
+#define TARGET_NR_ptrace 117
+#define TARGET_NR_sched_setparam 118
+#define TARGET_NR_sched_setscheduler 119
+#define TARGET_NR_sched_getscheduler 120
+#define TARGET_NR_sched_getparam 121
+#define TARGET_NR_sched_setaffinity 122
+#define TARGET_NR_sched_getaffinity 123
+#define TARGET_NR_sched_yield 124
+#define TARGET_NR_sched_get_priority_max 125
+#define TARGET_NR_sched_get_priority_min 126
+#define TARGET_NR_sched_rr_get_interval 127
+#define TARGET_NR_restart_syscall 128
+#define TARGET_NR_kill 129
+#define TARGET_NR_tkill 130
+#define TARGET_NR_tgkill 131
+#define TARGET_NR_sigaltstack 132
+#define TARGET_NR_rt_sigsuspend 133
+#define TARGET_NR_rt_sigaction 134
+#define TARGET_NR_rt_sigprocmask 135
+#define TARGET_NR_rt_sigpending 136
+#define TARGET_NR_rt_sigtimedwait 137
+#define TARGET_NR_rt_sigqueueinfo 138
+#define TARGET_NR_rt_sigreturn 139
+#define TARGET_NR_setpriority 140
+#define TARGET_NR_getpriority 141
+#define TARGET_NR_reboot 142
+#define TARGET_NR_setregid 143
+#define TARGET_NR_setgid 144
+#define TARGET_NR_setreuid 145
+#define TARGET_NR_setuid 146
+#define TARGET_NR_setresuid 147
+#define TARGET_NR_getresuid 148
+#define TARGET_NR_setresgid 149
+#define TARGET_NR_getresgid 150
+#define TARGET_NR_setfsuid 151
+#define TARGET_NR_setfsgid 152
+#define TARGET_NR_times 153
+#define TARGET_NR_setpgid 154
+#define TARGET_NR_getpgid 155
+#define TARGET_NR_getsid 156
+#define TARGET_NR_setsid 157
+#define TARGET_NR_getgroups 158
+#define TARGET_NR_setgroups 159
+#define TARGET_NR_uname 160
+#define TARGET_NR_sethostname 161
+#define TARGET_NR_setdomainname 162
+#define TARGET_NR_getrusage 165
+#define TARGET_NR_umask 166
+#define TARGET_NR_prctl 167
+#define TARGET_NR_getcpu 168
+#define TARGET_NR_gettimeofday 169
+#define TARGET_NR_settimeofday 170
+#define TARGET_NR_adjtimex 171
+#define TARGET_NR_getpid 172
+#define TARGET_NR_getppid 173
+#define TARGET_NR_getuid 174
+#define TARGET_NR_geteuid 175
+#define TARGET_NR_getgid 176
+#define TARGET_NR_getegid 177
+#define TARGET_NR_gettid 178
+#define TARGET_NR_sysinfo 179
+#define TARGET_NR_mq_open 180
+#define TARGET_NR_mq_unlink 181
+#define TARGET_NR_mq_timedsend 182
+#define TARGET_NR_mq_timedreceive 183
+#define TARGET_NR_mq_notify 184
+#define TARGET_NR_mq_getsetattr 185
+#define TARGET_NR_msgget 186
+#define TARGET_NR_msgctl 187
+#define TARGET_NR_msgrcv 188
+#define TARGET_NR_msgsnd 189
+#define TARGET_NR_semget 190
+#define TARGET_NR_semctl 191
+#define TARGET_NR_semtimedop 192
+#define TARGET_NR_semop 193
+#define TARGET_NR_shmget 194
+#define TARGET_NR_shmctl 195
+#define TARGET_NR_shmat 196
+#define TARGET_NR_shmdt 197
+#define TARGET_NR_socket 198
+#define TARGET_NR_socketpair 199
+#define TARGET_NR_bind 200
+#define TARGET_NR_listen 201
+#define TARGET_NR_accept 202
+#define TARGET_NR_connect 203
+#define TARGET_NR_getsockname 204
+#define TARGET_NR_getpeername 205
+#define TARGET_NR_sendto 206
+#define TARGET_NR_recvfrom 207
+#define TARGET_NR_setsockopt 208
+#define TARGET_NR_getsockopt 209
+#define TARGET_NR_shutdown 210
+#define TARGET_NR_sendmsg 211
+#define TARGET_NR_recvmsg 212
+#define TARGET_NR_readahead 213
+#define TARGET_NR_brk 214
+#define TARGET_NR_munmap 215
+#define TARGET_NR_mremap 216
+#define TARGET_NR_add_key 217
+#define TARGET_NR_request_key 218
+#define TARGET_NR_keyctl 219
+#define TARGET_NR_clone 220
+#define TARGET_NR_execve 221
+#define TARGET_NR_mmap 222
+#define TARGET_NR_fadvise64 223
+#define TARGET_NR_swapon 224
+#define TARGET_NR_swapoff 225
+#define TARGET_NR_mprotect 226
+#define TARGET_NR_msync 227
+#define TARGET_NR_mlock 228
+#define TARGET_NR_munlock 229
+#define TARGET_NR_mlockall 230
+#define TARGET_NR_munlockall 231
+#define TARGET_NR_mincore 232
+#define TARGET_NR_madvise 233
+#define TARGET_NR_remap_file_pages 234
+#define TARGET_NR_mbind 235
+#define TARGET_NR_get_mempolicy 236
+#define TARGET_NR_set_mempolicy 237
+#define TARGET_NR_migrate_pages 238
+#define TARGET_NR_move_pages 239
+#define TARGET_NR_rt_tgsigqueueinfo 240
+#define TARGET_NR_perf_event_open 241
+#define TARGET_NR_accept4 242
+#define TARGET_NR_recvmmsg 243
+#define TARGET_NR_arch_specific_syscall 244
+#define TARGET_NR_wait4 260
+#define TARGET_NR_prlimit64 261
+#define TARGET_NR_fanotify_init 262
+#define TARGET_NR_fanotify_mark 263
+#define TARGET_NR_name_to_handle_at 264
+#define TARGET_NR_open_by_handle_at 265
+#define TARGET_NR_clock_adjtime 266
+#define TARGET_NR_syncfs 267
+#define TARGET_NR_setns 268
+#define TARGET_NR_sendmmsg 269
+#define TARGET_NR_process_vm_readv 270
+#define TARGET_NR_process_vm_writev 271
+#define TARGET_NR_kcmp 272
+#define TARGET_NR_finit_module 273
+#define TARGET_NR_sched_setattr 274
+#define TARGET_NR_sched_getattr 275
+#define TARGET_NR_renameat2 276
+#define TARGET_NR_seccomp 277
+#define TARGET_NR_getrandom 278
+#define TARGET_NR_memfd_create 279
+#define TARGET_NR_bpf 280
+#define TARGET_NR_execveat 281
+#define TARGET_NR_userfaultfd 282
+#define TARGET_NR_membarrier 283
+#define TARGET_NR_mlock2 284
+#define TARGET_NR_copy_file_range 285
+#define TARGET_NR_preadv2 286
+#define TARGET_NR_pwritev2 287
+#define TARGET_NR_pkey_mprotect 288
+#define TARGET_NR_pkey_alloc 289
+#define TARGET_NR_pkey_free 290
+#define TARGET_NR_statx 291
+#define TARGET_NR_io_pgetevents 292
+#define TARGET_NR_rseq 293
+#define TARGET_NR_kexec_file_load 294
+#define TARGET_NR_pidfd_send_signal 424
+#define TARGET_NR_io_uring_setup 425
+#define TARGET_NR_io_uring_enter 426
+#define TARGET_NR_io_uring_register 427
+#define TARGET_NR_open_tree 428
+#define TARGET_NR_move_mount 429
+#define TARGET_NR_fsopen 430
+#define TARGET_NR_fsconfig 431
+#define TARGET_NR_fsmount 432
+#define TARGET_NR_fspick 433
+#define TARGET_NR_pidfd_open 434
+#define TARGET_NR_clone3 435
+#define TARGET_NR_close_range 436
+#define TARGET_NR_openat2 437
+#define TARGET_NR_pidfd_getfd 438
+#define TARGET_NR_faccessat2 439
+#define TARGET_NR_process_madvise 440
+#define TARGET_NR_epoll_pwait2 441
+#define TARGET_NR_mount_setattr 442
+#define TARGET_NR_quotactl_fd 443
+#define TARGET_NR_landlock_create_ruleset 444
+#define TARGET_NR_landlock_add_rule 445
+#define TARGET_NR_landlock_restrict_self 446
+#define TARGET_NR_process_mrelease 448
+#define TARGET_NR_futex_waitv 449
+#define TARGET_NR_set_mempolicy_home_node 450
+#define TARGET_NR_syscalls 451
+
+#endif /* LINUX_USER_LOONGARCH_SYSCALL_NR_H */
diff --git a/linux-user/loongarch64/target_syscall.h b/linux-user/loongarch64/target_syscall.h
new file mode 100644
index 0000000000..8b5de52124
--- /dev/null
+++ b/linux-user/loongarch64/target_syscall.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef LOONGARCH_TARGET_SYSCALL_H
+#define LOONGARCH_TARGET_SYSCALL_H
+
+#include "qemu/units.h"
+
+/*
+ * this struct defines the way the registers are stored on the
+ * stack during a system call.
+ */
+
+struct target_pt_regs {
+ /* Saved main processor registers. */
+ target_ulong regs[32];
+
+ /* Saved special registers. */
+ struct {
+ target_ulong era;
+ target_ulong badv;
+ target_ulong crmd;
+ target_ulong prmd;
+ target_ulong euen;
+ target_ulong ecfg;
+ target_ulong estat;
+ } csr;
+ target_ulong orig_a0;
+ target_ulong __last[0];
+};
+
+#define UNAME_MACHINE "loongarch64"
+#define UNAME_MINIMUM_RELEASE "5.19.0"
+
+#define TARGET_MCL_CURRENT 1
+#define TARGET_MCL_FUTURE 2
+#define TARGET_MCL_ONFAULT 4
+
+#define TARGET_FORCE_SHMLBA
+
+static inline abi_ulong target_shmlba(CPULoongArchState *env)
+{
+ return 64 * KiB;
+}
+
+#endif
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 4587b62ac9..85b0f33e91 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@ -74,7 +74,7 @@
|| defined(TARGET_M68K) || defined(TARGET_CRIS) \
|| defined(TARGET_S390X) || defined(TARGET_OPENRISC) \
|| defined(TARGET_NIOS2) || defined(TARGET_RISCV) \
- || defined(TARGET_XTENSA)
+ || defined(TARGET_XTENSA) || defined(TARGET_LOONGARCH64)
#define TARGET_IOC_SIZEBITS 14
#define TARGET_IOC_DIRBITS 2
@@ -2196,6 +2196,10 @@ struct target_stat64 {
uint64_t st_ino;
};
+#elif defined(TARGET_LOONGARCH64)
+
+/* LoongArch no newfstatat/fstat syscall. */
+
#else
#error unsupported CPU
#endif
diff --git a/scripts/gensyscalls.sh b/scripts/gensyscalls.sh
index 8fb450e3c9..a2f7664b7b 100755
--- a/scripts/gensyscalls.sh
+++ b/scripts/gensyscalls.sh
@@ -44,6 +44,7 @@ read_includes()
cpp -P -nostdinc -fdirectives-only \
-D_UAPI_ASM_$(upper ${arch})_BITSPERLONG_H \
+ -D__ASM_$(upper ${arch})_BITSPERLONG_H \
-D__BITS_PER_LONG=${bits} \
-I${linux}/arch/${arch}/include/uapi/ \
-I${linux}/include/uapi \
@@ -99,4 +100,5 @@ generate_syscall_nr openrisc 32 "$output/linux-user/openrisc/syscall_nr.h"
generate_syscall_nr riscv 32 "$output/linux-user/riscv/syscall32_nr.h"
generate_syscall_nr riscv 64 "$output/linux-user/riscv/syscall64_nr.h"
generate_syscall_nr hexagon 32 "$output/linux-user/hexagon/syscall_nr.h"
+generate_syscall_nr loongarch 64 "$output/linux-user/loongarch64/syscall_nr.h"
rm -fr "$TMP"
--
2.31.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v17 05/13] linux-user: Add LoongArch cpu_loop support
2022-06-16 12:15 [PATCH v17 00/13] Add LoongArch linux-user emulation support Song Gao
` (3 preceding siblings ...)
2022-06-16 12:16 ` [PATCH v17 04/13] linux-user: Add LoongArch syscall support Song Gao
@ 2022-06-16 12:16 ` Song Gao
2022-06-16 12:16 ` [PATCH v17 06/13] scripts: add loongarch64 binfmt config Song Gao
` (7 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Song Gao @ 2022-06-16 12:16 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson, laurent, gaosong, Xiaojuan Yang
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/loongarch64/cpu_loop.c | 96 +++++++++++++++++++++++++++++
linux-user/loongarch64/target_cpu.h | 34 ++++++++++
2 files changed, 130 insertions(+)
create mode 100644 linux-user/loongarch64/cpu_loop.c
create mode 100644 linux-user/loongarch64/target_cpu.h
diff --git a/linux-user/loongarch64/cpu_loop.c b/linux-user/loongarch64/cpu_loop.c
new file mode 100644
index 0000000000..894fdd111a
--- /dev/null
+++ b/linux-user/loongarch64/cpu_loop.c
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU LoongArch user cpu_loop.
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "qemu.h"
+#include "user-internals.h"
+#include "cpu_loop-common.h"
+#include "signal-common.h"
+
+void cpu_loop(CPULoongArchState *env)
+{
+ CPUState *cs = env_cpu(env);
+ int trapnr, si_code;
+ abi_long ret;
+
+ for (;;) {
+ cpu_exec_start(cs);
+ trapnr = cpu_exec(cs);
+ cpu_exec_end(cs);
+ process_queued_cpu_work(cs);
+
+ switch (trapnr) {
+ case EXCP_INTERRUPT:
+ /* just indicate that signals should be handled asap */
+ break;
+ case EXCCODE_SYS:
+ env->pc += 4;
+ ret = do_syscall(env, env->gpr[11],
+ env->gpr[4], env->gpr[5],
+ env->gpr[6], env->gpr[7],
+ env->gpr[8], env->gpr[9],
+ -1, -1);
+ if (ret == -QEMU_ERESTARTSYS) {
+ env->pc -= 4;
+ break;
+ }
+ if (ret == -QEMU_ESIGRETURN) {
+ /*
+ * Returning from a successful sigreturn syscall.
+ * Avoid clobbering register state.
+ */
+ break;
+ }
+ env->gpr[4] = ret;
+ break;
+ case EXCCODE_INE:
+ force_sig_fault(TARGET_SIGILL, 0, env->pc);
+ break;
+ case EXCCODE_FPE:
+ si_code = TARGET_FPE_FLTUNK;
+ if (GET_FP_CAUSE(env->fcsr0) & FP_INVALID) {
+ si_code = TARGET_FPE_FLTINV;
+ } else if (GET_FP_CAUSE(env->fcsr0) & FP_DIV0) {
+ si_code = TARGET_FPE_FLTDIV;
+ } else if (GET_FP_CAUSE(env->fcsr0) & FP_OVERFLOW) {
+ si_code = TARGET_FPE_FLTOVF;
+ } else if (GET_FP_CAUSE(env->fcsr0) & FP_UNDERFLOW) {
+ si_code = TARGET_FPE_FLTUND;
+ } else if (GET_FP_CAUSE(env->fcsr0) & FP_INEXACT) {
+ si_code = TARGET_FPE_FLTRES;
+ }
+ force_sig_fault(TARGET_SIGFPE, si_code, env->pc);
+ break;
+ case EXCP_DEBUG:
+ case EXCCODE_BRK:
+ force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc);
+ break;
+ case EXCCODE_BCE:
+ force_sig_fault(TARGET_SIGSYS, TARGET_SI_KERNEL, env->pc);
+ break;
+ case EXCP_ATOMIC:
+ cpu_exec_step_atomic(cs);
+ break;
+ default:
+ EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n",
+ trapnr);
+ exit(EXIT_FAILURE);
+ }
+ process_pending_signals(env);
+ }
+}
+
+void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
+{
+ int i;
+
+ for (i = 0; i < 32; i++) {
+ env->gpr[i] = regs->regs[i];
+ }
+ env->pc = regs->csr.era;
+
+}
diff --git a/linux-user/loongarch64/target_cpu.h b/linux-user/loongarch64/target_cpu.h
new file mode 100644
index 0000000000..a29af66156
--- /dev/null
+++ b/linux-user/loongarch64/target_cpu.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * LoongArch specific CPU ABI and functions for linux-user
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef LOONGARCH_TARGET_CPU_H
+#define LOONGARCH_TARGET_CPU_H
+
+static inline void cpu_clone_regs_child(CPULoongArchState *env,
+ target_ulong newsp, unsigned flags)
+{
+ if (newsp) {
+ env->gpr[3] = newsp;
+ }
+ env->gpr[4] = 0;
+}
+
+static inline void cpu_clone_regs_parent(CPULoongArchState *env,
+ unsigned flags)
+{
+}
+
+static inline void cpu_set_tls(CPULoongArchState *env, target_ulong newtls)
+{
+ env->gpr[2] = newtls;
+}
+
+static inline abi_ulong get_sp_from_cpustate(CPULoongArchState *state)
+{
+ return state->gpr[3];
+}
+#endif
--
2.31.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v17 06/13] scripts: add loongarch64 binfmt config
2022-06-16 12:15 [PATCH v17 00/13] Add LoongArch linux-user emulation support Song Gao
` (4 preceding siblings ...)
2022-06-16 12:16 ` [PATCH v17 05/13] linux-user: Add LoongArch cpu_loop support Song Gao
@ 2022-06-16 12:16 ` Song Gao
2022-06-16 12:16 ` [PATCH v17 07/13] target/loongarch: remove badaddr from CPULoongArch Song Gao
` (6 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Song Gao @ 2022-06-16 12:16 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson, laurent, gaosong, Xiaojuan Yang
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
scripts/qemu-binfmt-conf.sh | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/scripts/qemu-binfmt-conf.sh b/scripts/qemu-binfmt-conf.sh
index 9cb723f443..1f4e2cd19d 100755
--- a/scripts/qemu-binfmt-conf.sh
+++ b/scripts/qemu-binfmt-conf.sh
@@ -4,7 +4,7 @@
qemu_target_list="i386 i486 alpha arm armeb sparc sparc32plus sparc64 \
ppc ppc64 ppc64le m68k mips mipsel mipsn32 mipsn32el mips64 mips64el \
sh4 sh4eb s390x aarch64 aarch64_be hppa riscv32 riscv64 xtensa xtensaeb \
-microblaze microblazeel or1k x86_64 hexagon"
+microblaze microblazeel or1k x86_64 hexagon loongarch64"
i386_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x03\x00'
i386_mask='\xff\xff\xff\xff\xff\xfe\xfe\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff'
@@ -140,6 +140,10 @@ hexagon_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x
hexagon_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff'
hexagon_family=hexagon
+loongarch64_magic='\x7fELF\x02\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x02\x01'
+loongarch64_mask='\xff\xff\xff\xff\xff\xff\xff\xfc\x00\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff'
+loongarch64_family=loongarch
+
qemu_get_family() {
cpu=${HOST_ARCH:-$(uname -m)}
case "$cpu" in
--
2.31.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v17 07/13] target/loongarch: remove badaddr from CPULoongArch
2022-06-16 12:15 [PATCH v17 00/13] Add LoongArch linux-user emulation support Song Gao
` (5 preceding siblings ...)
2022-06-16 12:16 ` [PATCH v17 06/13] scripts: add loongarch64 binfmt config Song Gao
@ 2022-06-16 12:16 ` Song Gao
2022-06-18 2:48 ` Richard Henderson
2022-06-16 12:16 ` [PATCH v17 08/13] target/loongarch: Fix missing update CSR_BADV Song Gao
` (5 subsequent siblings)
12 siblings, 1 reply; 20+ messages in thread
From: Song Gao @ 2022-06-16 12:16 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson, laurent, gaosong, Xiaojuan Yang
We can use CSR_BADV to replace badaddr.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
---
target/loongarch/cpu.h | 2 --
target/loongarch/gdbstub.c | 2 +-
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 71a5036c3c..4b4fbcdc71 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -246,8 +246,6 @@ typedef struct CPUArchState {
uint64_t lladdr; /* LL virtual address compared against SC */
uint64_t llval;
- uint64_t badaddr;
-
/* LoongArch CSRs */
uint64_t CSR_CRMD;
uint64_t CSR_PRMD;
diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c
index 0c48834201..24e126fb2d 100644
--- a/target/loongarch/gdbstub.c
+++ b/target/loongarch/gdbstub.c
@@ -21,7 +21,7 @@ int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
} else if (n == 32) {
return gdb_get_regl(mem_buf, env->pc);
} else if (n == 33) {
- return gdb_get_regl(mem_buf, env->badaddr);
+ return gdb_get_regl(mem_buf, env->CSR_BADV);
}
return 0;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v17 07/13] target/loongarch: remove badaddr from CPULoongArch
2022-06-16 12:16 ` [PATCH v17 07/13] target/loongarch: remove badaddr from CPULoongArch Song Gao
@ 2022-06-18 2:48 ` Richard Henderson
0 siblings, 0 replies; 20+ messages in thread
From: Richard Henderson @ 2022-06-18 2:48 UTC (permalink / raw)
To: Song Gao, qemu-devel; +Cc: laurent, Xiaojuan Yang
On 6/16/22 05:16, Song Gao wrote:
> We can use CSR_BADV to replace badaddr.
>
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
> ---
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
> target/loongarch/cpu.h | 2 --
> target/loongarch/gdbstub.c | 2 +-
> 2 files changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
> index 71a5036c3c..4b4fbcdc71 100644
> --- a/target/loongarch/cpu.h
> +++ b/target/loongarch/cpu.h
> @@ -246,8 +246,6 @@ typedef struct CPUArchState {
> uint64_t lladdr; /* LL virtual address compared against SC */
> uint64_t llval;
>
> - uint64_t badaddr;
> -
> /* LoongArch CSRs */
> uint64_t CSR_CRMD;
> uint64_t CSR_PRMD;
> diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c
> index 0c48834201..24e126fb2d 100644
> --- a/target/loongarch/gdbstub.c
> +++ b/target/loongarch/gdbstub.c
> @@ -21,7 +21,7 @@ int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
> } else if (n == 32) {
> return gdb_get_regl(mem_buf, env->pc);
> } else if (n == 33) {
> - return gdb_get_regl(mem_buf, env->badaddr);
> + return gdb_get_regl(mem_buf, env->CSR_BADV);
> }
> return 0;
> }
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v17 08/13] target/loongarch: Fix missing update CSR_BADV
2022-06-16 12:15 [PATCH v17 00/13] Add LoongArch linux-user emulation support Song Gao
` (6 preceding siblings ...)
2022-06-16 12:16 ` [PATCH v17 07/13] target/loongarch: remove badaddr from CPULoongArch Song Gao
@ 2022-06-16 12:16 ` Song Gao
2022-06-18 2:49 ` Richard Henderson
2022-06-16 12:16 ` [PATCH v17 09/13] target/loongarch: Fix helper_asrtle_d/asrtgt_d raise wrong exception Song Gao
` (4 subsequent siblings)
12 siblings, 1 reply; 20+ messages in thread
From: Song Gao @ 2022-06-16 12:16 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson, laurent, gaosong, Xiaojuan Yang
loongarch_cpu_do_interrupt() should update CSR_BADV for some EXCCODE.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
---
target/loongarch/cpu.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 4c8f96bc3a..e32d4cc269 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -171,18 +171,20 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
cause = cs->exception_index;
update_badinstr = 0;
break;
- case EXCCODE_ADEM:
case EXCCODE_SYS:
case EXCCODE_BRK:
+ case EXCCODE_INE:
+ case EXCCODE_IPE:
+ case EXCCODE_FPE:
+ env->CSR_BADV = env->pc;
+ QEMU_FALLTHROUGH;
+ case EXCCODE_ADEM:
case EXCCODE_PIL:
case EXCCODE_PIS:
case EXCCODE_PME:
case EXCCODE_PNR:
case EXCCODE_PNX:
case EXCCODE_PPI:
- case EXCCODE_INE:
- case EXCCODE_IPE:
- case EXCCODE_FPE:
cause = cs->exception_index;
break;
default:
--
2.31.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v17 09/13] target/loongarch: Fix helper_asrtle_d/asrtgt_d raise wrong exception
2022-06-16 12:15 [PATCH v17 00/13] Add LoongArch linux-user emulation support Song Gao
` (7 preceding siblings ...)
2022-06-16 12:16 ` [PATCH v17 08/13] target/loongarch: Fix missing update CSR_BADV Song Gao
@ 2022-06-16 12:16 ` Song Gao
2022-06-18 2:50 ` Richard Henderson
2022-06-16 12:16 ` [PATCH v17 10/13] target/loongarch: remove unused include hw/loader.h Song Gao
` (3 subsequent siblings)
12 siblings, 1 reply; 20+ messages in thread
From: Song Gao @ 2022-06-16 12:16 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson, laurent, gaosong, Xiaojuan Yang
Raising EXCCODE_BCE instead of EXCCODE_ADEM for helper_asrtle_d/asrtgt_d.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
---
target/loongarch/cpu.c | 2 ++
target/loongarch/op_helper.c | 4 ++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index e32d4cc269..0013582a3a 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -51,6 +51,7 @@ static const char * const excp_names[] = {
[EXCCODE_IPE] = "Instruction privilege error",
[EXCCODE_FPE] = "Floating Point Exception",
[EXCCODE_DBP] = "Debug breakpoint",
+ [EXCCODE_BCE] = "Bound Check Exception",
};
const char *loongarch_exception_name(int32_t exception)
@@ -176,6 +177,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
case EXCCODE_INE:
case EXCCODE_IPE:
case EXCCODE_FPE:
+ case EXCCODE_BCE:
env->CSR_BADV = env->pc;
QEMU_FALLTHROUGH;
case EXCCODE_ADEM:
diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c
index d87049851f..df049cec59 100644
--- a/target/loongarch/op_helper.c
+++ b/target/loongarch/op_helper.c
@@ -49,14 +49,14 @@ target_ulong helper_bitswap(target_ulong v)
void helper_asrtle_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
{
if (rj > rk) {
- do_raise_exception(env, EXCCODE_ADEM, GETPC());
+ do_raise_exception(env, EXCCODE_BCE, 0);
}
}
void helper_asrtgt_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
{
if (rj <= rk) {
- do_raise_exception(env, EXCCODE_ADEM, GETPC());
+ do_raise_exception(env, EXCCODE_BCE, 0);
}
}
--
2.31.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v17 09/13] target/loongarch: Fix helper_asrtle_d/asrtgt_d raise wrong exception
2022-06-16 12:16 ` [PATCH v17 09/13] target/loongarch: Fix helper_asrtle_d/asrtgt_d raise wrong exception Song Gao
@ 2022-06-18 2:50 ` Richard Henderson
0 siblings, 0 replies; 20+ messages in thread
From: Richard Henderson @ 2022-06-18 2:50 UTC (permalink / raw)
To: Song Gao, qemu-devel; +Cc: laurent, Xiaojuan Yang
On 6/16/22 05:16, Song Gao wrote:
> Raising EXCCODE_BCE instead of EXCCODE_ADEM for helper_asrtle_d/asrtgt_d.
>
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
> ---
> target/loongarch/cpu.c | 2 ++
> target/loongarch/op_helper.c | 4 ++--
> 2 files changed, 4 insertions(+), 2 deletions(-)
"Raise" not "Raising".
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
>
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index e32d4cc269..0013582a3a 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -51,6 +51,7 @@ static const char * const excp_names[] = {
> [EXCCODE_IPE] = "Instruction privilege error",
> [EXCCODE_FPE] = "Floating Point Exception",
> [EXCCODE_DBP] = "Debug breakpoint",
> + [EXCCODE_BCE] = "Bound Check Exception",
> };
>
> const char *loongarch_exception_name(int32_t exception)
> @@ -176,6 +177,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
> case EXCCODE_INE:
> case EXCCODE_IPE:
> case EXCCODE_FPE:
> + case EXCCODE_BCE:
> env->CSR_BADV = env->pc;
> QEMU_FALLTHROUGH;
> case EXCCODE_ADEM:
> diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c
> index d87049851f..df049cec59 100644
> --- a/target/loongarch/op_helper.c
> +++ b/target/loongarch/op_helper.c
> @@ -49,14 +49,14 @@ target_ulong helper_bitswap(target_ulong v)
> void helper_asrtle_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
> {
> if (rj > rk) {
> - do_raise_exception(env, EXCCODE_ADEM, GETPC());
> + do_raise_exception(env, EXCCODE_BCE, 0);
> }
> }
>
> void helper_asrtgt_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
> {
> if (rj <= rk) {
> - do_raise_exception(env, EXCCODE_ADEM, GETPC());
> + do_raise_exception(env, EXCCODE_BCE, 0);
> }
> }
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v17 10/13] target/loongarch: remove unused include hw/loader.h
2022-06-16 12:15 [PATCH v17 00/13] Add LoongArch linux-user emulation support Song Gao
` (8 preceding siblings ...)
2022-06-16 12:16 ` [PATCH v17 09/13] target/loongarch: Fix helper_asrtle_d/asrtgt_d raise wrong exception Song Gao
@ 2022-06-16 12:16 ` Song Gao
2022-06-18 2:51 ` Richard Henderson
2022-06-16 12:16 ` [PATCH v17 11/13] target/loongarch: Adjust functions and structure to support user-mode Song Gao
` (2 subsequent siblings)
12 siblings, 1 reply; 20+ messages in thread
From: Song Gao @ 2022-06-16 12:16 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson, laurent, gaosong, Xiaojuan Yang
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
---
target/loongarch/cpu.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 0013582a3a..bf163a8dce 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -18,7 +18,6 @@
#include "fpu/softfloat-helpers.h"
#include "cpu-csr.h"
#include "sysemu/reset.h"
-#include "hw/loader.h"
const char * const regnames[32] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
--
2.31.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v17 11/13] target/loongarch: Adjust functions and structure to support user-mode
2022-06-16 12:15 [PATCH v17 00/13] Add LoongArch linux-user emulation support Song Gao
` (9 preceding siblings ...)
2022-06-16 12:16 ` [PATCH v17 10/13] target/loongarch: remove unused include hw/loader.h Song Gao
@ 2022-06-16 12:16 ` Song Gao
2022-06-18 2:56 ` Richard Henderson
2022-06-16 12:16 ` [PATCH v17 12/13] default-configs: Add loongarch linux-user support Song Gao
2022-06-16 12:16 ` [PATCH v17 13/13] target/loongarch: Update README Song Gao
12 siblings, 1 reply; 20+ messages in thread
From: Song Gao @ 2022-06-16 12:16 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson, laurent, gaosong, Xiaojuan Yang
Some functions and member of the structure are different with softmmu-mode
So we need adjust them to support user-mode.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
---
target/loongarch/cpu.c | 21 ++++++++++-
target/loongarch/cpu.h | 6 ++++
target/loongarch/helper.h | 2 ++
.../insn_trans/trans_privileged.c.inc | 36 +++++++++++++++++++
target/loongarch/internals.h | 2 ++
target/loongarch/op_helper.c | 6 ++++
6 files changed, 72 insertions(+), 1 deletion(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index bf163a8dce..47c0bdd1ac 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -82,6 +82,7 @@ static void loongarch_cpu_set_pc(CPUState *cs, vaddr value)
env->pc = value;
}
+#ifndef CONFIG_USER_ONLY
#include "hw/loongarch/virt.h"
void loongarch_cpu_set_irq(void *opaque, int irq, int level)
@@ -295,6 +296,7 @@ static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
return false;
}
+#endif
#ifdef CONFIG_TCG
static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
@@ -309,6 +311,9 @@ static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
static bool loongarch_cpu_has_work(CPUState *cs)
{
+#ifdef CONFIG_USER_ONLY
+ return true;
+#else
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
CPULoongArchState *env = &cpu->env;
bool has_work = false;
@@ -319,6 +324,7 @@ static bool loongarch_cpu_has_work(CPUState *cs)
}
return has_work;
+#endif
}
static void loongarch_la464_initfn(Object *obj)
@@ -467,7 +473,9 @@ static void loongarch_cpu_reset(DeviceState *dev)
env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0);
}
+#ifndef CONFIG_USER_ONLY
env->pc = 0x1c000000;
+#endif
restore_fp_status(env);
cs->exception_index = -1;
@@ -498,6 +506,7 @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp)
lacc->parent_realize(dev, errp);
}
+#ifndef CONFIG_USER_ONLY
static void loongarch_qemu_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
@@ -532,13 +541,16 @@ static const MemoryRegionOps loongarch_qemu_ops = {
.max_access_size = 8,
},
};
+#endif
static void loongarch_cpu_init(Object *obj)
{
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
- CPULoongArchState *env = &cpu->env;
cpu_set_cpustate_pointers(cpu);
+
+#ifndef CONFIG_USER_ONLY
+ CPULoongArchState *env = &cpu->env;
qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS);
timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL,
&loongarch_constant_timer_cb, cpu);
@@ -548,6 +560,7 @@ static void loongarch_cpu_init(Object *obj)
memory_region_init_io(&env->iocsr_mem, OBJECT(cpu), &loongarch_qemu_ops,
NULL, "iocsr_misc", 0x428);
memory_region_add_subregion(&env->system_iocsr, 0, &env->iocsr_mem);
+#endif
}
static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model)
@@ -615,18 +628,22 @@ static struct TCGCPUOps loongarch_tcg_ops = {
.initialize = loongarch_translate_init,
.synchronize_from_tb = loongarch_cpu_synchronize_from_tb,
+#ifndef CONFIG_USER_ONLY
.tlb_fill = loongarch_cpu_tlb_fill,
.cpu_exec_interrupt = loongarch_cpu_exec_interrupt,
.do_interrupt = loongarch_cpu_do_interrupt,
.do_transaction_failed = loongarch_cpu_do_transaction_failed,
+#endif
};
#endif /* CONFIG_TCG */
+#ifndef CONFIG_USER_ONLY
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps loongarch_sysemu_ops = {
.get_phys_page_debug = loongarch_cpu_get_phys_page_debug,
};
+#endif
static void loongarch_cpu_class_init(ObjectClass *c, void *data)
{
@@ -642,8 +659,10 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
cc->has_work = loongarch_cpu_has_work;
cc->dump_state = loongarch_cpu_dump_state;
cc->set_pc = loongarch_cpu_set_pc;
+#ifndef CONFIG_USER_ONLY
dc->vmsd = &vmstate_loongarch_cpu;
cc->sysemu_ops = &loongarch_sysemu_ops;
+#endif
cc->disas_set_info = loongarch_cpu_disas_set_info;
cc->gdb_read_register = loongarch_cpu_gdb_read_register;
cc->gdb_write_register = loongarch_cpu_gdb_write_register;
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 4b4fbcdc71..d141ec9b5d 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -301,6 +301,7 @@ typedef struct CPUArchState {
uint64_t CSR_DERA;
uint64_t CSR_DSAVE;
+#ifndef CONFIG_USER_ONLY
LoongArchTLB tlb[LOONGARCH_TLB_MAX];
AddressSpace address_space_iocsr;
@@ -308,6 +309,7 @@ typedef struct CPUArchState {
MemoryRegion iocsr_mem;
bool load_elf;
uint64_t elf_address;
+#endif
} CPULoongArchState;
/**
@@ -358,12 +360,16 @@ struct LoongArchCPUClass {
static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
{
+#ifdef CONFIG_USER_ONLY
+ return MMU_USER_IDX;
+#else
uint8_t pg = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG);
if (!pg) {
return MMU_DA_IDX;
}
return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
+#endif
}
static inline void cpu_get_tb_cpu_state(CPULoongArchState *env,
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 85c11a60d4..cbbe008f32 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -95,6 +95,7 @@ DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_1(rdtime_d, i64, env)
+#ifndef CONFIG_USER_ONLY
/* CSRs helper */
DEF_HELPER_1(csrrd_pgd, i64, env)
DEF_HELPER_1(csrrd_tval, i64, env)
@@ -128,3 +129,4 @@ DEF_HELPER_4(lddir, tl, env, tl, tl, i32)
DEF_HELPER_4(ldpte, void, env, tl, tl, i32)
DEF_HELPER_1(ertn, void, env)
DEF_HELPER_1(idle, void, env)
+#endif
diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/loongarch/insn_trans/trans_privileged.c.inc
index 53596c4f77..9c4dcbfcfb 100644
--- a/target/loongarch/insn_trans/trans_privileged.c.inc
+++ b/target/loongarch/insn_trans/trans_privileged.c.inc
@@ -7,6 +7,41 @@
#include "cpu-csr.h"
+#ifdef CONFIG_USER_ONLY
+
+#define GEN_FALSE_TRANS(name) \
+static bool trans_##name(DisasContext *ctx, arg_##name * a) \
+{ \
+ return false; \
+}
+
+GEN_FALSE_TRANS(csrrd)
+GEN_FALSE_TRANS(csrwr)
+GEN_FALSE_TRANS(csrxchg)
+GEN_FALSE_TRANS(iocsrrd_b)
+GEN_FALSE_TRANS(iocsrrd_h)
+GEN_FALSE_TRANS(iocsrrd_w)
+GEN_FALSE_TRANS(iocsrrd_d)
+GEN_FALSE_TRANS(iocsrwr_b)
+GEN_FALSE_TRANS(iocsrwr_h)
+GEN_FALSE_TRANS(iocsrwr_w)
+GEN_FALSE_TRANS(iocsrwr_d)
+GEN_FALSE_TRANS(tlbsrch)
+GEN_FALSE_TRANS(tlbrd)
+GEN_FALSE_TRANS(tlbwr)
+GEN_FALSE_TRANS(tlbfill)
+GEN_FALSE_TRANS(tlbclr)
+GEN_FALSE_TRANS(tlbflush)
+GEN_FALSE_TRANS(invtlb)
+GEN_FALSE_TRANS(cacop)
+GEN_FALSE_TRANS(ldpte)
+GEN_FALSE_TRANS(lddir)
+GEN_FALSE_TRANS(ertn)
+GEN_FALSE_TRANS(dbcl)
+GEN_FALSE_TRANS(idle)
+
+#else
+
typedef void (*GenCSRRead)(TCGv dest, TCGv_ptr env);
typedef void (*GenCSRWrite)(TCGv dest, TCGv_ptr env, TCGv src);
@@ -464,3 +499,4 @@ static bool trans_idle(DisasContext *ctx, arg_idle *a)
ctx->base.is_jmp = DISAS_NORETURN;
return true;
}
+#endif
diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
index 9d50fbdd81..ea227362b6 100644
--- a/target/loongarch/internals.h
+++ b/target/loongarch/internals.h
@@ -33,6 +33,7 @@ const char *loongarch_exception_name(int32_t exception);
void restore_fp_status(CPULoongArchState *env);
+#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_loongarch_cpu;
void loongarch_cpu_set_irq(void *opaque, int irq, int level);
@@ -48,6 +49,7 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
bool probe, uintptr_t retaddr);
hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+#endif /* !CONFIG_USER_ONLY */
int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n);
int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n);
diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c
index df049cec59..4b429b6699 100644
--- a/target/loongarch/op_helper.c
+++ b/target/loongarch/op_helper.c
@@ -86,6 +86,9 @@ target_ulong helper_cpucfg(CPULoongArchState *env, target_ulong rj)
uint64_t helper_rdtime_d(CPULoongArchState *env)
{
+#ifdef CONFIG_USER_ONLY
+ return cpu_get_host_ticks();
+#else
uint64_t plv;
LoongArchCPU *cpu = env_archcpu(env);
@@ -95,8 +98,10 @@ uint64_t helper_rdtime_d(CPULoongArchState *env)
}
return cpu_loongarch_get_constant_timer_counter(cpu);
+#endif
}
+#ifndef CONFIG_USER_ONLY
void helper_ertn(CPULoongArchState *env)
{
uint64_t csr_pplv, csr_pie;
@@ -131,3 +136,4 @@ void helper_idle(CPULoongArchState *env)
cs->halted = 1;
do_raise_exception(env, EXCP_HLT, 0);
}
+#endif
--
2.31.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v17 11/13] target/loongarch: Adjust functions and structure to support user-mode
2022-06-16 12:16 ` [PATCH v17 11/13] target/loongarch: Adjust functions and structure to support user-mode Song Gao
@ 2022-06-18 2:56 ` Richard Henderson
0 siblings, 0 replies; 20+ messages in thread
From: Richard Henderson @ 2022-06-18 2:56 UTC (permalink / raw)
To: Song Gao, qemu-devel; +Cc: laurent, Xiaojuan Yang
On 6/16/22 05:16, Song Gao wrote:
> Some functions and member of the structure are different with softmmu-mode
> So we need adjust them to support user-mode.
>
> Signed-off-by: Song Gao<gaosong@loongson.cn>
> Signed-off-by: Xiaojuan Yang<yangxiaojuan@loongson.cn>
> ---
> target/loongarch/cpu.c | 21 ++++++++++-
> target/loongarch/cpu.h | 6 ++++
> target/loongarch/helper.h | 2 ++
> .../insn_trans/trans_privileged.c.inc | 36 +++++++++++++++++++
> target/loongarch/internals.h | 2 ++
> target/loongarch/op_helper.c | 6 ++++
> 6 files changed, 72 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v17 12/13] default-configs: Add loongarch linux-user support
2022-06-16 12:15 [PATCH v17 00/13] Add LoongArch linux-user emulation support Song Gao
` (10 preceding siblings ...)
2022-06-16 12:16 ` [PATCH v17 11/13] target/loongarch: Adjust functions and structure to support user-mode Song Gao
@ 2022-06-16 12:16 ` Song Gao
2022-06-16 12:16 ` [PATCH v17 13/13] target/loongarch: Update README Song Gao
12 siblings, 0 replies; 20+ messages in thread
From: Song Gao @ 2022-06-16 12:16 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, laurent, gaosong, Xiaojuan Yang, WANG Xuerui
This patch adds loongarch64 linux-user default configs file.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: WANG Xuerui <git@xen0n.name>
---
configs/targets/loongarch64-linux-user.mak | 3 +++
1 file changed, 3 insertions(+)
create mode 100644 configs/targets/loongarch64-linux-user.mak
diff --git a/configs/targets/loongarch64-linux-user.mak b/configs/targets/loongarch64-linux-user.mak
new file mode 100644
index 0000000000..7d1b964020
--- /dev/null
+++ b/configs/targets/loongarch64-linux-user.mak
@@ -0,0 +1,3 @@
+# Default configuration for loongarch64-linux-user
+TARGET_ARCH=loongarch64
+TARGET_BASE_ARCH=loongarch
--
2.31.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v17 13/13] target/loongarch: Update README
2022-06-16 12:15 [PATCH v17 00/13] Add LoongArch linux-user emulation support Song Gao
` (11 preceding siblings ...)
2022-06-16 12:16 ` [PATCH v17 12/13] default-configs: Add loongarch linux-user support Song Gao
@ 2022-06-16 12:16 ` Song Gao
12 siblings, 0 replies; 20+ messages in thread
From: Song Gao @ 2022-06-16 12:16 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson, laurent, gaosong, Xiaojuan Yang
Add linux-user emulation introduction
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/README | 39 +++++++++++++++++++++++++++++++++++++--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/README b/target/loongarch/README
index 4dcd0f1682..9f5edd10c8 100644
--- a/target/loongarch/README
+++ b/target/loongarch/README
@@ -24,9 +24,9 @@
Download cross-tools.
- wget https://github.com/loongson/build-tools/releases/latest/download/loongarch64-clfs-20211202-cross-tools.tar.xz
+ wget https://github.com/loongson/build-tools/releases/download/2022.05.29/loongarch64-clfs-5.0-cross-tools-gcc-full.tar.xz
- tar -vxf loongarch64-clfs-20211202-cross-tools.tar.xz -C /opt
+ tar -vxf loongarch64-clfs-5.0-cross-tools-gcc-full.tar.xz -C /opt
Config cross-tools env.
@@ -60,5 +60,40 @@
./build/qemu-system-loongarch64 -machine virt -m 4G -cpu Loongson-3A5000 -smp 1 -kernel build/tests/tcg/loongarch64-softmmu/hello -monitor none -display none -chardev file,path=hello.out,id=output -serial chardev:output
+- Linux-user emulation
+
+ We already support Linux user emulation. We can use LoongArch cross-tools to build LoongArch executables on X86 machines,
+ and We can also use qemu-loongarch64 to run LoongArch executables.
+
+ 1. Config cross-tools env.
+
+ see System emulation.
+
+ 2. Test tests/tcg/multiarch.
+
+ ./configure --static --prefix=/usr --disable-werror --target-list="loongarch64-linux-user" --enable-debug
+
+ cd build
+
+ make && make check-tcg
+
+ 3. Run LoongArch system basic command with loongarch-clfs-system.
+
+ - Config clfs env.
+
+ wget https://github.com/loongson/build-tools/releases/download/2022.05.29/loongarch64-clfs-system-5.0.tar.bz2
+
+ tar -vxf loongarch64-clfs-system-5.0.tar.bz2 -C /opt/clfs
+
+ cp /opt/clfs/lib64/ld-linux-loongarch-lp64d.so.1 /lib64
+
+ export LD_LIBRARY_PATH="/opt/clfs/lib64"
+
+ - Run LoongArch system basic command.
+
+ ./qemu-loongarch64 /opt/clfs/usr/bin/bash
+ ./qemu-loongarch64 /opt/clfs/usr/bin/ls
+ ./qemu-loongarch64 /opt/clfs/usr/bin/pwd
+
- Note.
We can get the latest LoongArch documents or LoongArch tools at https://github.com/loongson/
--
2.31.1
^ permalink raw reply related [flat|nested] 20+ messages in thread