From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49338) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YkqP0-0006gr-46 for qemu-devel@nongnu.org; Wed, 22 Apr 2015 04:53:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YkqOw-0002He-0S for qemu-devel@nongnu.org; Wed, 22 Apr 2015 04:53:02 -0400 Received: from mx1.redhat.com ([209.132.183.28]:49395) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YkqOv-0002Gy-P7 for qemu-devel@nongnu.org; Wed, 22 Apr 2015 04:52:57 -0400 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id t3M8qulH020415 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Wed, 22 Apr 2015 04:52:56 -0400 Message-ID: <55376163.4070107@redhat.com> Date: Wed, 22 Apr 2015 10:52:51 +0200 From: Laszlo Ersek MIME-Version: 1.0 References: <1429521560-2743-1-git-send-email-kraxel@redhat.com> <1429521560-2743-5-git-send-email-kraxel@redhat.com> <55365C33.2090101@redhat.com> <1429628650.21164.24.camel@nilsson.home.kraxel.org> <1429690157.14806.43.camel@nilsson.home.kraxel.org> In-Reply-To: <1429690157.14806.43.camel@nilsson.home.kraxel.org> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 5/6] [wip] tseg, part1, not (yet) tested List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Gerd Hoffmann Cc: pbonzini@redhat.com, qemu-devel@nongnu.org, mst@redhat.com On 04/22/15 10:09, Gerd Hoffmann wrote: > Hi, > >> tseg is just normal ram (yes, located at the end of memory), but (once >> tseg is enabled) only cpus in smm mode are allowed to access it. >> Likewise busmaster dma access is rejected, so non-smm code can't use the >> sata controller to access this indirectly. > > Update: Seems tseg can be anywhere, there is a "tseg memory base" > register @ 0xac in pci config space. > > Placing it at the end of memory is just what the bios is supposed to do > by default. And it makes sense to place it there. > > > This register contains the base address of TSEG DRAM memory. BIOS > determines the base of TSEG memory by subtracting the TSEG size (PCI > Device 0, offset 9Eh, bits 2:1) from graphics GTT stolen base (PCI > Device 0, offset A8h, bits 31:20). > > Once D_LCK has been set, these bits becomes read only. > > > "GTT stolen base" equals "top of below-4g memory" for us because we > emulate the chipset variant without graphics in qemu. Thanks, that sounds good. So, as far as I understand, no changes to what we've discussed thus far. But, I have another question -- am I allowed to use "top of below-4g memory" directly, as discussed earlier, or should I use the above PCI registers? The tseg size will actually come from me (because I'll select it), but the top I could take from "top of below-4g memory" (preferably, see earlier), or reading the 0xA8 register. Unless, of course 0xA8 won't be implemented at all, *because* "we emulate the chipset variant without graphics in qemu." In other words, if the 0xA8 register is dependent on the integrated graphics, then I don't have a question. :) Thanks! Laszlo