From: Paolo Bonzini <pbonzini@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>,
Christopher Covington <christopher.covington@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [RFC 5/5] arm: Simplify cycle counter
Date: Mon, 04 May 2015 11:54:59 +0200 [thread overview]
Message-ID: <554741F3.1070705@redhat.com> (raw)
In-Reply-To: <CAFEAcA-ycjab-8xCe4WcXVsG=aoTLfSc1B_aFxy_EbAs3ndHEw@mail.gmail.com>
On 01/05/2015 00:02, Peter Maydell wrote:
> On 30 April 2015 at 22:33, Christopher Covington
> <christopher.covington@linaro.org> wrote:
>> On Apr 30, 2015 2:28 PM, "Peter Maydell" <peter.maydell@linaro.org> wrote:
>>> Are you really really sure the _raw function is the correct one?
>>> Nowhere else in the codebase calls it except the other wrappers
>>> in cpu.c which provide a sane view of the instruction count...
>>> (I suspect cpu_get_icount_raw() should really be static.)
>>
>> I thought it wasn't being used because it was new, having been introduced by
>> Pavel Dovgalyuk's determinism patches.
>>
>> When you talk about sanity, what would this patch make insane?
The right function is cpu_get_ticks(). This one works without icount as
well.
At the top there is:
if (use_icount) {
return cpu_get_icount();
}
and perhaps it would be correct to use cpu_get_icount_raw() if you do
not want the cycle counter to increase in halted state. But at least
x86 wants it to increase.
Paolo
The
>> instructions per second and cycles per second that would result? If so, what
>> if seconds/timer ticks were changed in the same patch to be derived from the
>> instruction count. All of this could potentially only apply with -icount
>> specified.
>
> I don't really know for certain how the code here works, but
> it makes me very dubious when I see a function that is being
> used literally nowhere else in any other target CPU, and
> where every other code path to it goes via taking a lock.
>
> Paolo: can you suggest what the right function to call to implement
> a cycle counter is?
>
> thanks
> -- PMM
>
next prev parent reply other threads:[~2015-05-04 9:55 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-30 18:14 [Qemu-devel] [RFC 1/5] arm64: Add PMINTENCLR_EL1 Christopher Covington
2015-04-30 18:14 ` [Qemu-devel] [RFC 2/5] arm64: Add PMOVSCLR_EL0 register Christopher Covington
2015-04-30 18:14 ` [Qemu-devel] [RFC 3/5] arm64: Add PMUSERENR_EL0 register Christopher Covington
2015-04-30 18:14 ` [Qemu-devel] [RFC 4/5] arm64: Unmask PMU bits in debug feature register Christopher Covington
2015-04-30 18:14 ` [Qemu-devel] [RFC 5/5] arm: Simplify cycle counter Christopher Covington
2015-04-30 18:27 ` Peter Maydell
2015-04-30 21:33 ` Christopher Covington
2015-04-30 22:02 ` Peter Maydell
2015-05-04 9:54 ` Paolo Bonzini [this message]
2015-05-01 1:24 ` Peter Crosthwaite
2015-05-01 14:35 ` Christopher Covington
2015-05-06 14:05 ` Peter Crosthwaite
2015-05-06 15:38 ` Peter Maydell
2015-09-24 19:43 ` [Qemu-devel] [PATCH] target-arm: Use common CPU cycle infrastructure Christopher Covington
2015-09-28 22:05 ` Alistair Francis
2015-09-29 14:07 ` Christopher Covington
2015-10-02 16:44 ` Christopher Covington
2015-10-02 16:56 ` Peter Maydell
2015-10-02 17:25 ` Peter Crosthwaite
2015-10-02 18:08 ` Peter Maydell
2015-10-02 18:14 ` Peter Crosthwaite
2015-10-02 19:25 ` Christopher Covington
2015-10-02 19:56 ` Peter Crosthwaite
2015-10-02 20:48 ` Christopher Covington
2015-10-02 22:41 ` Peter Maydell
2015-10-05 14:09 ` Paolo Bonzini
2015-10-05 14:11 ` Peter Maydell
2015-10-05 14:27 ` Paolo Bonzini
2015-10-06 12:49 ` Peter Maydell
2015-10-06 12:58 ` Paolo Bonzini
2015-10-06 13:06 ` Peter Maydell
2015-10-06 13:10 ` Paolo Bonzini
2015-10-13 20:53 ` Peter Maydell
2015-10-14 12:10 ` Christopher Covington
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