From: Richard Henderson <rth@twiddle.net>
To: Alvise Rigo <a.rigo@virtualopensystems.com>, qemu-devel@nongnu.org
Cc: mttcg@greensocs.com, jani.kokkonen@huawei.com,
tech@virtualopensystems.com, claudio.fontana@huawei.com
Subject: Re: [Qemu-devel] [RFC 1/5] exec: Add new exclusive bitmap to ram_list
Date: Thu, 07 May 2015 10:12:25 -0700 [thread overview]
Message-ID: <554B9CF9.7040707@twiddle.net> (raw)
In-Reply-To: <1430926687-25875-2-git-send-email-a.rigo@virtualopensystems.com>
On 05/06/2015 08:38 AM, Alvise Rigo wrote:
> The purpose of this new bitmap is to flag the memory pages that are in
> the middle of LL/SC operations (after a LL, before a SC).
> For all these pages, the corresponding TLB entries will be generated
> in such a way to force the slow-path.
>
> The accessors to this bitmap are currently not atomic, but they have to
> be so in a real multi-threading TCG.
>
> Suggested-by: Jani Kokkonen <jani.kokkonen@huawei.com>
> Suggested-by: Claudio Fontana <claudio.fontana@huawei.com>
> Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com>
> ---
> include/exec/cpu-defs.h | 2 ++
> include/exec/memory.h | 3 ++-
> include/exec/ram_addr.h | 19 ++++++++++++++++++-
> 3 files changed, 22 insertions(+), 2 deletions(-)
>
> diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
> index 0ca6f0b..d12cb4c 100644
> --- a/include/exec/cpu-defs.h
> +++ b/include/exec/cpu-defs.h
> @@ -123,5 +123,7 @@ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
> #define CPU_COMMON \
> /* soft mmu support */ \
> CPU_COMMON_TLB \
> + /* true if in the middle of a LoadLink/StoreConditional */ \
> + bool ll_sc_context; \
Belongs to a different patch?
r~
next prev parent reply other threads:[~2015-05-07 17:12 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-06 15:38 [Qemu-devel] [RFC 0/5] Slow-path for atomic instruction translation Alvise Rigo
2015-05-06 15:38 ` [Qemu-devel] [RFC 1/5] exec: Add new exclusive bitmap to ram_list Alvise Rigo
2015-05-07 17:12 ` Richard Henderson [this message]
2015-05-11 7:48 ` alvise rigo
2015-05-06 15:38 ` [Qemu-devel] [RFC 2/5] Add new TLB_EXCL flag Alvise Rigo
2015-05-07 17:25 ` Richard Henderson
2015-05-11 7:47 ` alvise rigo
2015-05-06 15:38 ` [Qemu-devel] [RFC 3/5] softmmu: Add helpers for a new slow-path Alvise Rigo
2015-05-07 17:56 ` Richard Henderson
2015-05-11 8:07 ` alvise rigo
2015-05-06 15:38 ` [Qemu-devel] [RFC 4/5] tcg-op: create new TCG qemu_ldlink and qemu_stcond instructions Alvise Rigo
2015-05-07 17:58 ` Richard Henderson
2015-05-11 8:12 ` alvise rigo
2015-05-06 15:38 ` [Qemu-devel] [RFC 5/5] target-arm: translate: implement qemu_ldlink and qemu_stcond ops Alvise Rigo
2015-05-06 15:51 ` [Qemu-devel] [RFC 0/5] Slow-path for atomic instruction translation Paolo Bonzini
2015-05-06 16:00 ` Mark Burton
2015-05-06 16:21 ` alvise rigo
2015-05-06 15:55 ` Mark Burton
2015-05-06 16:19 ` alvise rigo
2015-05-06 16:20 ` Mark Burton
2015-05-08 15:22 ` Alex Bennée
2015-05-11 9:08 ` alvise rigo
2015-05-08 18:29 ` Emilio G. Cota
2015-05-11 9:10 ` alvise rigo
2015-05-26 21:51 ` Emilio G. Cota
2015-05-27 7:20 ` alvise rigo
2015-05-27 8:51 ` Alex Bennée
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