From: Richard Henderson <rth@twiddle.net>
To: Alvise Rigo <a.rigo@virtualopensystems.com>, qemu-devel@nongnu.org
Cc: mttcg@greensocs.com, jani.kokkonen@huawei.com,
tech@virtualopensystems.com, claudio.fontana@huawei.com
Subject: Re: [Qemu-devel] [RFC 3/5] softmmu: Add helpers for a new slow-path
Date: Thu, 07 May 2015 10:56:30 -0700 [thread overview]
Message-ID: <554BA74E.9060206@twiddle.net> (raw)
In-Reply-To: <1430926687-25875-4-git-send-email-a.rigo@virtualopensystems.com>
On 05/06/2015 08:38 AM, Alvise Rigo wrote:
> +#define DATA_SIZE (1 << SHIFT)
> +
> +#if DATA_SIZE == 8
> +#define SUFFIX q
> +#define LSUFFIX q
> +#define SDATA_TYPE int64_t
> +#define DATA_TYPE uint64_t
Duplicating all of the stuff from softmmu_template.h is Just Wrong.
> +/* For the benefit of TCG generated code, we want to avoid the complication
> + of ABI-specific return type promotion and always return a value extended
> + to the register size of the host. This is tcg_target_long, except in the
> + case of a 32-bit host and 64-bit data, and for that we always have
> + uint64_t. Don't bother with this widened value for SOFTMMU_CODE_ACCESS. */
...
> +uint32_t helper_le_stcond_name(CPUArchState *env, target_ulong addr,
> + DATA_TYPE val, int mmu_idx, uintptr_t retaddr)
You didn't even read the comment above re the return type.
> + /* Another vCPU has accessed the memory after the LoadLink or not link
> + * has been previously set. */
> + ret = 1;
> + goto out;
> + }
> +
> + helper_st_legacy(env, addr, val, mmu_idx, retaddr);
> +
> + /* Set the page as dirty to avoid the creation of TLB entries with the
> + * TLB_EXCL bit set. */
> + cpu_physical_memory_set_excl_dirty(ram_addr);
> +
> + /* The StoreConditional succeeded */
> + ret = 0;
How did you come up with 0 == success, 1 = failure? Is this an arm-ism?
r~
next prev parent reply other threads:[~2015-05-07 17:56 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-06 15:38 [Qemu-devel] [RFC 0/5] Slow-path for atomic instruction translation Alvise Rigo
2015-05-06 15:38 ` [Qemu-devel] [RFC 1/5] exec: Add new exclusive bitmap to ram_list Alvise Rigo
2015-05-07 17:12 ` Richard Henderson
2015-05-11 7:48 ` alvise rigo
2015-05-06 15:38 ` [Qemu-devel] [RFC 2/5] Add new TLB_EXCL flag Alvise Rigo
2015-05-07 17:25 ` Richard Henderson
2015-05-11 7:47 ` alvise rigo
2015-05-06 15:38 ` [Qemu-devel] [RFC 3/5] softmmu: Add helpers for a new slow-path Alvise Rigo
2015-05-07 17:56 ` Richard Henderson [this message]
2015-05-11 8:07 ` alvise rigo
2015-05-06 15:38 ` [Qemu-devel] [RFC 4/5] tcg-op: create new TCG qemu_ldlink and qemu_stcond instructions Alvise Rigo
2015-05-07 17:58 ` Richard Henderson
2015-05-11 8:12 ` alvise rigo
2015-05-06 15:38 ` [Qemu-devel] [RFC 5/5] target-arm: translate: implement qemu_ldlink and qemu_stcond ops Alvise Rigo
2015-05-06 15:51 ` [Qemu-devel] [RFC 0/5] Slow-path for atomic instruction translation Paolo Bonzini
2015-05-06 16:00 ` Mark Burton
2015-05-06 16:21 ` alvise rigo
2015-05-06 15:55 ` Mark Burton
2015-05-06 16:19 ` alvise rigo
2015-05-06 16:20 ` Mark Burton
2015-05-08 15:22 ` Alex Bennée
2015-05-11 9:08 ` alvise rigo
2015-05-08 18:29 ` Emilio G. Cota
2015-05-11 9:10 ` alvise rigo
2015-05-26 21:51 ` Emilio G. Cota
2015-05-27 7:20 ` alvise rigo
2015-05-27 8:51 ` Alex Bennée
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