From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46247) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yro8M-00071D-W5 for qemu-devel@nongnu.org; Mon, 11 May 2015 09:52:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yro8I-0008K7-Qm for qemu-devel@nongnu.org; Mon, 11 May 2015 09:52:38 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:26133) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yro8I-0008Cd-KX for qemu-devel@nongnu.org; Mon, 11 May 2015 09:52:34 -0400 Message-ID: <5550B417.1030007@imgtec.com> Date: Mon, 11 May 2015 14:52:23 +0100 From: Leon Alrae MIME-Version: 1.0 References: <1431343850-46198-1-git-send-email-yongbok.kim@imgtec.com> <1431343850-46198-3-git-send-email-yongbok.kim@imgtec.com> <5550AB66.5010503@imgtec.com> In-Reply-To: <5550AB66.5010503@imgtec.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 2/2] target-mips: Misaligned memory accesses for MSA List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Yongbok Kim , qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Hi Yongbok, On 11/05/2015 14:15, Yongbok Kim wrote: > Hi > I have implemented this to have a flag which isn't that nice. > > The thing is that the fact misaligned accesses of MSA LD/ST should be allowed in R5 cores > while all other instructions are not allowed. > Therefore it is required which types of instruction is triggering the misaligned accesses. > > Initially I tried to fetch the instructions from the mips_cpu_do_unaligned_access() callback, > but if in certain case that the LD/ST address and PC are having same TLB indexes it goes wrong. > > I also tried to increase mmu_idx to avoid this problem but that requires anyway a flag as it is not > able to pass mmu_idx to cpu_{ld,st}XX_XXX(). (cpu_{ld,st}XX_XXX() are calling cpu_mmu_index() to get mmu_idx). > > I could use host address directly via {ld,st}xx_p() but then mmio will be left alone to be solved. > Perhaps another flag for the only case of R5 + MSA + MMIO. > > I might able to change all the generic load/store macros such as cpu_ldst_template.h and > softmmu_template.h to pass the misalignment information. > However that would be a huge work impacting all the architectures. > > Do you have any other thought or suggestion for this? Or this flag would be the necessary evil? I haven't reviewed this patch yet, but have you considered using always byte-by-byte accesses for misaligned MSA loads/stores? The flag wouldn't be required and also I suspect that we would benefit from the fast path. Thanks, Leon