From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43663) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YsH4S-0001hE-H0 for qemu-devel@nongnu.org; Tue, 12 May 2015 16:46:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YsH4R-00043y-Df for qemu-devel@nongnu.org; Tue, 12 May 2015 16:46:32 -0400 Received: from cantor2.suse.de ([195.135.220.15]:37917 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YsH4Q-00043Q-WC for qemu-devel@nongnu.org; Tue, 12 May 2015 16:46:31 -0400 Message-ID: <555266A4.7050100@suse.de> Date: Tue, 12 May 2015 22:46:28 +0200 From: Alexander Graf MIME-Version: 1.0 References: <1431462031-46912-1-git-send-email-agraf@suse.de> <5552622D.6020305@twiddle.net> In-Reply-To: <5552622D.6020305@twiddle.net> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2] s390x: Add laa and laag instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson , qemu-devel@nongnu.org On 05/12/2015 10:27 PM, Richard Henderson wrote: > On 05/12/2015 01:20 PM, Alexander Graf wrote: >> +static void in2_m2_32s_atomic(DisasContext *s, DisasFields *f, DisasOps *o) >> +{ >> + /* XXX should reserve the address */ >> + in2_m2_32s(s, f, o); >> +} >> +#define SPEC_in2_m2_32s_atomic 0 >> + >> +static void in2_m2_64_atomic(DisasContext *s, DisasFields *f, DisasOps *o) >> +{ >> + /* XXX should reserve the address */ >> + in2_m2_64(s, f, o); >> +} >> +#define SPEC_in2_m2_64_atomic 0 >> + > I think these should save the address in o->addr1 so that you don't have to > recompute it in the wout functions. But I suppose you basically mean something like this? Alex diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 73f2de3..8a30c8f 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -4074,25 +4074,17 @@ static void wout_m2_32(DisasContext *s, DisasFields *f, DisasOps *o) static void wout_m2_32_r1_atomic(DisasContext *s, DisasFields *f, DisasOps *o) { - TCGv_i64 a2 = get_a2(s, f); - /* XXX release reservation */ - tcg_gen_qemu_st32(o->out, a2, get_mem_index(s)); + tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s)); store_reg32_i64(get_field(f, r1), o->in2); - - tcg_temp_free_i64(a2); } #define SPEC_wout_m2_32_r1_atomic 0 static void wout_m2_64_r1_atomic(DisasContext *s, DisasFields *f, DisasOps *o) { - TCGv_i64 a2 = get_a2(s, f); - /* XXX release reservation */ - tcg_gen_qemu_st64(o->out, a2, get_mem_index(s)); + tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s)); store_reg(get_field(f, r1), o->in2); - - tcg_temp_free_i64(a2); } #define SPEC_wout_m2_64_r1_atomic 0 @@ -4519,14 +4511,18 @@ static void in2_mri2_64(DisasContext *s, DisasFields *f, DisasOps *o) static void in2_m2_32s_atomic(DisasContext *s, DisasFields *f, DisasOps *o) { /* XXX should reserve the address */ - in2_m2_32s(s, f, o); + o->addr1 = get_a2(s, f); + o->in2 = tcg_temp_new_i64(); + tcg_gen_qemu_ld32s(o->in2, o->addr1, get_mem_index(s)); } #define SPEC_in2_m2_32s_atomic 0 static void in2_m2_64_atomic(DisasContext *s, DisasFields *f, DisasOps *o) { /* XXX should reserve the address */ - in2_m2_64(s, f, o); + o->addr1 = get_a2(s, f); + o->in2 = tcg_temp_new_i64(); + tcg_gen_qemu_ld64(o->in2, o->addr1, get_mem_index(s)); } #define SPEC_in2_m2_64_atomic 0