From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55826) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YsUxb-0005Ro-2m for qemu-devel@nongnu.org; Wed, 13 May 2015 07:36:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YsUxX-0001i0-Ia for qemu-devel@nongnu.org; Wed, 13 May 2015 07:36:23 -0400 Received: from mx1.redhat.com ([209.132.183.28]:43916) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YsUxX-0001ho-Aj for qemu-devel@nongnu.org; Wed, 13 May 2015 07:36:19 -0400 Message-ID: <5553372A.60409@redhat.com> Date: Wed, 13 May 2015 13:36:10 +0200 From: Paolo Bonzini MIME-Version: 1.0 References: <20140907014747.GA12586@zapo.iiNet> <20150513064105.GZ10142@toto> <55531946.9080501@redhat.com> <20150513112104.GC13061@toto> In-Reply-To: <20150513112104.GC13061@toto> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] Supporting multiple CPU AddressSpaces and memory transaction attributes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Edgar E. Iglesias" Cc: Peter Maydell , Peter Crosthwaite , Richard Henderson , QEMU Developers , Greg Bellows On 13/05/2015 13:21, Edgar E. Iglesias wrote: > > It was not clear to me if CPUs should hook into the iommu notification > system or if we should make the iommu notification code signal changes > through AS change notifications. > > The latter would be easy to get right I guess but we wouldn't be > able to have any granularity in the flushing so performance could > be better if the CPU somehow knows what parts have changed. I think it's CPUs that should hook and flush their TLBs. Paolo