From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52146) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YwFCy-0004qF-DB for qemu-devel@nongnu.org; Sat, 23 May 2015 15:35:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YwFCv-0006rS-70 for qemu-devel@nongnu.org; Sat, 23 May 2015 15:35:44 -0400 Received: from mail-pd0-x229.google.com ([2607:f8b0:400e:c02::229]:33918) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YwFCu-0006rO-NX for qemu-devel@nongnu.org; Sat, 23 May 2015 15:35:41 -0400 Received: by pdbki1 with SMTP id ki1so1259466pdb.1 for ; Sat, 23 May 2015 12:35:39 -0700 (PDT) Sender: Richard Henderson Message-ID: <5560D607.7080101@twiddle.net> Date: Sat, 23 May 2015 12:33:27 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1432243971-26417-1-git-send-email-aurelien@aurel32.net> <555E512F.4050603@twiddle.net> <20150523075906.GA25414@aurel32.net> In-Reply-To: <20150523075906.GA25414@aurel32.net> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] target-s390x: fix LOAD MULTIPLE instruction on page boundary List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, Alexander Graf On 05/23/2015 12:59 AM, Aurelien Jarno wrote: > On 2015-05-21 14:42, Richard Henderson wrote: >> Hmm. Seems to be un/under-specified in the PoO. That said, > > There is a small sentence in the PoO, in chapter "Program Execution", > section "Sequence of Storage Reference": > > It can normally be assumed that the execution of > each instruction occurs as an indivisible event. Ah, I didn't think to look in a different chapter. ;-) >> It would be nice to know if there ought to be similar up-front access checking >> for STM, to avoid errant partial stores. > > I have just checked, the same is also true for STM instructions, though > it's probably more difficult to fix that in QEMU. Maybe we need a way to > check if a load/store will succeed, preferably without using a helper. I did just suggest a new helper in the "unaligned stores for mips r6" thread. Therein we provide a probe_write helper that does assert that the given page is writable, or raise the usual exception. It leaves the TLB updated, so a subsequent write should take the fast path. It should be easy enough to extend that with an opcode so that we can implement this for s390 as probe_write addr + n * size - 1 qemu_st r0, addr qemu_st r1, addr + 1*size ... Hopefully for the edge case where both pages are unmapped, producing an exception pointing to the last byte, rather than the first byte, is acceptable. r~