From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50516) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ywt1z-00069w-AZ for qemu-devel@nongnu.org; Mon, 25 May 2015 10:07:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ywt1v-0000VM-5g for qemu-devel@nongnu.org; Mon, 25 May 2015 10:07:03 -0400 Received: from mout.web.de ([212.227.15.3]:61448) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ywt1u-0000Sr-L3 for qemu-devel@nongnu.org; Mon, 25 May 2015 10:06:59 -0400 Message-ID: <55632C7A.8010107@web.de> Date: Mon, 25 May 2015 16:06:50 +0200 From: Jan Kiszka MIME-Version: 1.0 References: <5561EB59.5000407@web.de> <5563225B.60200@redhat.com> In-Reply-To: <5563225B.60200@redhat.com> Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="kdieE8XPNk9ATKWJSKOjUvV4Rg4MRlVM9" Subject: [Qemu-devel] [PATCH v2] i386: Introduce ARAT CPU feature List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , Eduardo Habkost Cc: qemu-devel , kvm This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --kdieE8XPNk9ATKWJSKOjUvV4Rg4MRlVM9 Content-Type: text/plain; charset=iso-8859-15 Content-Transfer-Encoding: quoted-printable From: Jan Kiszka ARAT signals that the APIC timer does not stop in power saving states. As our APICs are emulated, it's fine to expose this feature to guests, at least when asking for KVM host features or with CPU types that include the flag. The exact model number that introduced the feature is not known, but reports can be found that it's at least available since Sandy Bridge. Signed-off-by: Jan Kiszka --- Changes in v2: - remove feature from Intel CPU types in compat machines hw/i386/pc_piix.c | 10 ++++++++++ target-i386/cpu.c | 33 ++++++++++++++++++++++++++++++++- target-i386/cpu.h | 3 +++ target-i386/kvm.c | 2 ++ 4 files changed, 47 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 212e263..83133fa 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -312,6 +312,16 @@ static void pc_init_pci(MachineState *machine) =20 static void pc_compat_2_3(MachineState *machine) { + x86_cpu_compat_set_features("Westmere", FEAT_6_EAX, 0, CPUID_6_EAX_A= RAT); + x86_cpu_compat_set_features("SandyBridge", FEAT_6_EAX, 0, + CPUID_6_EAX_ARAT); + x86_cpu_compat_set_features("IvyBridge", FEAT_6_EAX, 0, CPUID_6_EAX_= ARAT); + x86_cpu_compat_set_features("Haswell-noTSX", FEAT_6_EAX, 0, + CPUID_6_EAX_ARAT); + x86_cpu_compat_set_features("Haswell", FEAT_6_EAX, 0, CPUID_6_EAX_AR= AT); + x86_cpu_compat_set_features("Broadwell-noTSC", FEAT_6_EAX, 0, + CPUID_6_EAX_ARAT); + x86_cpu_compat_set_features("Broadwell", FEAT_6_EAX, 0, CPUID_6_EAX_= ARAT); } =20 static void pc_compat_2_2(MachineState *machine) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 3305e09..e435a08 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -284,6 +284,17 @@ static const char *cpuid_xsave_feature_name[] =3D { NULL, NULL, NULL, NULL, }; =20 +static const char *cpuid_6_feature_name[] =3D { + NULL, NULL, "arat", NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, +}; + #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) @@ -339,6 +350,7 @@ static const char *cpuid_xsave_feature_name[] =3D { CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, CPUID_7_0_EBX_RDSEED */ #define TCG_APM_FEATURES 0 +#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT =20 =20 typedef struct FeatureWordInfo { @@ -408,6 +420,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WOR= DS] =3D { .cpuid_reg =3D R_EAX, .tcg_features =3D 0, }, + [FEAT_6_EAX] =3D { + .feat_names =3D cpuid_6_feature_name, + .cpuid_eax =3D 6, .cpuid_reg =3D R_EAX, + .tcg_features =3D TCG_6_EAX_FEATURES, + }, }; =20 typedef struct X86RegisterInfo32 { @@ -1001,6 +1018,8 @@ static X86CPUDefinition builtin_x86_defs[] =3D { CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, .features[FEAT_8000_0001_ECX] =3D CPUID_EXT3_LAHF_LM, + .features[FEAT_6_EAX] =3D + CPUID_6_EAX_ARAT, .xlevel =3D 0x8000000A, .model_id =3D "Westmere E56xx/L56xx/X56xx (Nehalem-C)", }, @@ -1030,6 +1049,8 @@ static X86CPUDefinition builtin_x86_defs[] =3D { CPUID_EXT3_LAHF_LM, .features[FEAT_XSAVE] =3D CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] =3D + CPUID_6_EAX_ARAT, .xlevel =3D 0x8000000A, .model_id =3D "Intel Xeon E312xx (Sandy Bridge)", }, @@ -1062,6 +1083,8 @@ static X86CPUDefinition builtin_x86_defs[] =3D { CPUID_EXT3_LAHF_LM, .features[FEAT_XSAVE] =3D CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] =3D + CPUID_6_EAX_ARAT, .xlevel =3D 0x8000000A, .model_id =3D "Intel Xeon E3-12xx v2 (Ivy Bridge)", }, @@ -1096,6 +1119,8 @@ static X86CPUDefinition builtin_x86_defs[] =3D { CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVP= CID, .features[FEAT_XSAVE] =3D CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] =3D + CPUID_6_EAX_ARAT, .xlevel =3D 0x8000000A, .model_id =3D "Intel Core Processor (Haswell, no TSX)", }, { @@ -1130,6 +1155,8 @@ static X86CPUDefinition builtin_x86_defs[] =3D { CPUID_7_0_EBX_RTM, .features[FEAT_XSAVE] =3D CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] =3D + CPUID_6_EAX_ARAT, .xlevel =3D 0x8000000A, .model_id =3D "Intel Core Processor (Haswell)", }, @@ -1166,6 +1193,8 @@ static X86CPUDefinition builtin_x86_defs[] =3D { CPUID_7_0_EBX_SMAP, .features[FEAT_XSAVE] =3D CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] =3D + CPUID_6_EAX_ARAT, .xlevel =3D 0x8000000A, .model_id =3D "Intel Core Processor (Broadwell, no TSX)", }, @@ -1202,6 +1231,8 @@ static X86CPUDefinition builtin_x86_defs[] =3D { CPUID_7_0_EBX_SMAP, .features[FEAT_XSAVE] =3D CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] =3D + CPUID_6_EAX_ARAT, .xlevel =3D 0x8000000A, .model_id =3D "Intel Core Processor (Broadwell)", }, @@ -2358,7 +2389,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, break; case 6: /* Thermal and Power Leaf */ - *eax =3D 0; + *eax =3D env->features[FEAT_6_EAX]; *ebx =3D 0; *ecx =3D 0; *edx =3D 0; diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 4ee12ca..800158e 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -412,6 +412,7 @@ typedef enum FeatureWord { FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ FEAT_SVM, /* CPUID[8000_000A].EDX */ FEAT_XSAVE, /* CPUID[EAX=3D0xd,ECX=3D1].EAX */ + FEAT_6_EAX, /* CPUID[6].EAX */ FEATURE_WORDS, } FeatureWord; =20 @@ -577,6 +578,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_XSAVE_XGETBV1 (1U << 2) #define CPUID_XSAVE_XSAVES (1U << 3) =20 +#define CPUID_6_EAX_ARAT (1U << 2) + /* CPUID[0x80000007].EDX flags: */ #define CPUID_APM_INVTSC (1U << 8) =20 diff --git a/target-i386/kvm.c b/target-i386/kvm.c index a26d25a..b786359 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -233,6 +233,8 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, ui= nt32_t function, if (!kvm_irqchip_in_kernel()) { ret &=3D ~CPUID_EXT_X2APIC; } + } else if (function =3D=3D 6 && reg =3D=3D R_EAX) { + ret |=3D CPUID_6_EAX_ARAT; /* safe to allow because of emulated = APIC */ } else if (function =3D=3D 0x80000001 && reg =3D=3D R_EDX) { /* On Intel, kvm returns cpuid according to the Intel spec, * so add missing bits according to the AMD spec: --=20 2.1.4 --kdieE8XPNk9ATKWJSKOjUvV4Rg4MRlVM9 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEARECAAYFAlVjLHoACgkQitSsb3rl5xS2EgCgrwT571vV8Ml59HlJBv9OxnhQ uNEAoOj4S1Gd+V4W2Zvxw9w/v+yoSpQk =Wa/M -----END PGP SIGNATURE----- --kdieE8XPNk9ATKWJSKOjUvV4Rg4MRlVM9--